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Searched refs:WatermarkRow (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu_helper.c726 table->WatermarkRow[1][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
730 table->WatermarkRow[1][i].MaxClock = in smu_set_watermarks_for_clocks_ranges()
734 table->WatermarkRow[1][i].MinUclk = in smu_set_watermarks_for_clocks_ranges()
738 table->WatermarkRow[1][i].MaxUclk = in smu_set_watermarks_for_clocks_ranges()
742 table->WatermarkRow[1][i].WmSetting = (uint8_t) in smu_set_watermarks_for_clocks_ranges()
747 table->WatermarkRow[0][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
751 table->WatermarkRow[0][i].MaxClock = in smu_set_watermarks_for_clocks_ranges()
755 table->WatermarkRow[0][i].MinUclk = in smu_set_watermarks_for_clocks_ranges()
759 table->WatermarkRow[0][i].MaxUclk = in smu_set_watermarks_for_clocks_ranges()
763 table->WatermarkRow[0][i].WmSetting = (uint8_t) in smu_set_watermarks_for_clocks_ranges()
Dsmu_helper.h46 struct watermark_row_generic_t WatermarkRow[2][4]; member
Dsmu10_hwmgr.c1244 table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0; in smu10_set_watermarks_for_clocks_ranges()
1247 table->WatermarkRow[WM_SOCCLK][i].WmType = (uint8_t)0; in smu10_set_watermarks_for_clocks_ranges()
/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c932 table->WatermarkRow[WM_DCFCLK][i].MinClock = in renoir_set_watermarks_table()
934 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in renoir_set_watermarks_table()
936 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in renoir_set_watermarks_table()
938 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in renoir_set_watermarks_table()
941 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in renoir_set_watermarks_table()
943 table->WatermarkRow[WM_DCFCLK][i].WmType = in renoir_set_watermarks_table()
948 table->WatermarkRow[WM_SOCCLK][i].MinClock = in renoir_set_watermarks_table()
950 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in renoir_set_watermarks_table()
952 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in renoir_set_watermarks_table()
954 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in renoir_set_watermarks_table()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr.c362 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
363 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
364 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entri… in dcn3_notify_wm_ranges()
365 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entri… in dcn3_notify_wm_ranges()
366 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].WmSetting = i; in dcn3_notify_wm_ranges()
367 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries… in dcn3_notify_wm_ranges()
Ddcn30_clk_mgr_smu_msg.h78 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/drivers/gpu/drm/amd/pm/inc/
Dsmu10_driver_if.h70 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
Dsmu12_driver_if.h73 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
Dsmu9_driver_if.h347 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
Dsmu11_driver_if.h698 WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES]; member
Dsmu11_driver_if_navi10.h948 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
Dsmu11_driver_if_sienna_cichlid.h1069 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dnavi10_ppt.c1629 table->WatermarkRow[WM_DCEFCLK][i].MinClock = in navi10_set_watermarks_table()
1631 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = in navi10_set_watermarks_table()
1633 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = in navi10_set_watermarks_table()
1635 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = in navi10_set_watermarks_table()
1638 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = in navi10_set_watermarks_table()
1643 table->WatermarkRow[WM_SOCCLK][i].MinClock = in navi10_set_watermarks_table()
1645 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in navi10_set_watermarks_table()
1647 table->WatermarkRow[WM_SOCCLK][i].MinUclk = in navi10_set_watermarks_table()
1649 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = in navi10_set_watermarks_table()
1652 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in navi10_set_watermarks_table()
Dsienna_cichlid_ppt.c1460 table->WatermarkRow[WM_DCEFCLK][i].MinClock = in sienna_cichlid_set_watermarks_table()
1462 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = in sienna_cichlid_set_watermarks_table()
1464 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = in sienna_cichlid_set_watermarks_table()
1466 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = in sienna_cichlid_set_watermarks_table()
1469 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = in sienna_cichlid_set_watermarks_table()
1474 table->WatermarkRow[WM_SOCCLK][i].MinClock = in sienna_cichlid_set_watermarks_table()
1476 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in sienna_cichlid_set_watermarks_table()
1478 table->WatermarkRow[WM_SOCCLK][i].MinUclk = in sienna_cichlid_set_watermarks_table()
1480 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = in sienna_cichlid_set_watermarks_table()
1483 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in sienna_cichlid_set_watermarks_table()
/drivers/gpu/drm/amd/pm/inc/vega12/
Dsmu9_driver_if.h591 WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES]; member