Home
last modified time | relevance | path

Searched refs:_addr (Results 1 – 25 of 28) sorted by relevance

12

/drivers/staging/iio/meter/
Dmeter.h9 #define IIO_DEV_ATTR_CURRENT_A_OFFSET(_mode, _show, _store, _addr) \ argument
10 IIO_DEVICE_ATTR(current_a_offset, _mode, _show, _store, _addr)
12 #define IIO_DEV_ATTR_CURRENT_B_OFFSET(_mode, _show, _store, _addr) \ argument
13 IIO_DEVICE_ATTR(current_b_offset, _mode, _show, _store, _addr)
15 #define IIO_DEV_ATTR_CURRENT_C_OFFSET(_mode, _show, _store, _addr) \ argument
16 IIO_DEVICE_ATTR(current_c_offset, _mode, _show, _store, _addr)
18 #define IIO_DEV_ATTR_VOLT_A_OFFSET(_mode, _show, _store, _addr) \ argument
19 IIO_DEVICE_ATTR(volt_a_offset, _mode, _show, _store, _addr)
21 #define IIO_DEV_ATTR_VOLT_B_OFFSET(_mode, _show, _store, _addr) \ argument
22 IIO_DEVICE_ATTR(volt_b_offset, _mode, _show, _store, _addr)
[all …]
/drivers/staging/iio/frequency/
Ddds.h14 #define IIO_DEV_ATTR_FREQ(_channel, _num, _mode, _show, _store, _addr) \ argument
16 _mode, _show, _store, _addr)
29 #define IIO_DEV_ATTR_FREQSYMBOL(_channel, _mode, _show, _store, _addr) \ argument
31 _mode, _show, _store, _addr)
37 #define IIO_DEV_ATTR_PHASE(_channel, _num, _mode, _show, _store, _addr) \ argument
39 _mode, _show, _store, _addr)
52 #define IIO_DEV_ATTR_PHASESYMBOL(_channel, _mode, _show, _store, _addr) \ argument
54 _mode, _show, _store, _addr)
60 #define IIO_DEV_ATTR_PINCONTROL_EN(_channel, _mode, _show, _store, _addr)\ argument
62 _mode, _show, _store, _addr)
[all …]
/drivers/gpu/drm/nouveau/include/nvkm/core/
Dmemory.h76 u32 _addr = (a), _data = nvkm_ro32((o), _addr); \
77 nvkm_wo32((o), _addr, (_data & ~(m)) | (d)); \
88 u32 _addr = (a), _size = (s) >> 2, *_data = (void *)(p); \
90 *(_data++) = nvkm_ro32((o), _addr); \
91 _addr += 4; \
96 u32 _addr = (a), _size = (s) >> 2, *_data = (void *)(p); \
98 nvkm_wo32((o), _addr, *(_data++)); \
99 _addr += 4; \
Ddevice.h267 u32 _addr = (a), _temp = nvkm_rd32(_device, _addr); \
268 nvkm_wr32(_device, _addr, (_temp & ~(m)) | (v)); \
/drivers/iio/adc/
Dltc2497-core.c107 #define LTC2497_CHAN(_chan, _addr, _ds_name) { \ argument
111 .address = (_addr | (_chan / 2) | ((_chan & 1) ? LTC2497_SIGN : 0)), \
117 #define LTC2497_CHAN_DIFF(_chan, _addr) { \ argument
120 .channel = (_chan) * 2 + ((_addr) & LTC2497_SIGN ? 1 : 0), \
121 .channel2 = (_chan) * 2 + ((_addr) & LTC2497_SIGN ? 0 : 1),\
122 .address = (_addr | _chan), \
Dti-ads1015.c137 #define ADS1015_V_CHAN(_chan, _addr) { \ argument
140 .address = _addr, \
145 .scan_index = _addr, \
158 #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) { \ argument
162 .address = _addr, \
168 .scan_index = _addr, \
181 #define ADS1115_V_CHAN(_chan, _addr) { \ argument
184 .address = _addr, \
189 .scan_index = _addr, \
201 #define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) { \ argument
[all …]
Dxilinx-xadc-core.c1009 #define XADC_CHAN_TEMP(_chan, _scan_index, _addr) { \ argument
1013 .address = (_addr), \
1030 #define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) { \ argument
1034 .address = (_addr), \
1042 .sign = ((_addr) == XADC_REG_VREFN) ? 's' : 'u', \
/drivers/iio/pressure/
Dzpa2326_i2c.c33 #define ZPA2326_SA0(_addr) (_addr & BIT(0)) in zpa2326_i2c_hwid() argument
/drivers/gpu/drm/nouveau/include/nvif/
Dobject.h67 u32 _addr = (b), _data = nvif_rd32(__object, _addr); \
68 nvif_wr32(__object, _addr, (_data & ~(c)) | (d)); \
/drivers/net/ethernet/brocade/bna/
Dbna.h29 #define BNA_SET_DMA_ADDR(_addr, _bna_dma_addr) \ argument
32 cpu_to_be64((u64)(_addr)); \
41 #define BNA_GET_DMA_ADDR(_bna_dma_addr, _addr) \ argument
43 (_addr) = ((((u64)ntohl((_bna_dma_addr)->msb))) << 32) \
/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
Dvmm.h289 u64 _addr = ((BASE) + MAP->off); \
301 FILL(VMM, PT, PTEI, _ptes, MAP, _addr); \
339 const u64 _addr = (m)->addr + _pteo; \
340 VMM_SPAM((v), " %010llx %016llx%016llx"f, _addr, (hi), (lo), ##a); \
/drivers/iio/light/
Dcm3323.c52 #define CM3323_COLOR_CHANNEL(_color, _addr) { \ argument
58 .address = _addr, \
Dtcs3414.c63 #define TCS3414_CHANNEL(_color, _si, _addr) { \ argument
70 .address = _addr, \
Dtcs3472.c91 #define TCS3472_CHANNEL(_color, _si, _addr) { \ argument
98 .address = _addr, \
Das73211.c110 #define AS73211_COLOR_CHANNEL(_color, _si, _addr) { \ argument
123 .address = _addr, \
Dltr501.c560 #define LTR501_INTENSITY_CHANNEL(_idx, _addr, _mod, _shared, \ argument
564 .address = (_addr), \
/drivers/iio/chemical/
Dpms7003.c172 #define PMS7003_CHAN(_index, _mod, _addr) { \ argument
176 .address = _addr, \
Datlas-sensor.c139 #define ATLAS_CONCENTRATION_CHANNEL(_idx, _addr) \ argument
144 .address = _addr, \
/drivers/iio/accel/
Dmxc4005.c273 #define MXC4005_CHANNEL(_axis, _addr) { \ argument
277 .address = _addr, \
/drivers/usb/gadget/udc/
Dpxa27x_udc.h263 #define PXA_EP_DEF(_idx, _addr, dir, _type, maxpkt, _config, iface, altset) \ argument
268 .dir_in = dir, .addr = _addr, \
/drivers/iommu/
Dmtk_iommu.c139 dma_addr_t _addr = iova; \
140 ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\
/drivers/parisc/
Dpdc_stable.c102 #define PDCSPATH_ENTRY(_addr, _name) \ argument
105 .addr = _addr, \
/drivers/regulator/
Dab8500.c1044 #define REG_INIT(_id, _bank, _addr, _mask) \ argument
1047 .addr = _addr, \
/drivers/power/supply/
Dsbs-battery.c84 #define SBS_DATA(_psp, _addr, _min_value, _max_value) { \ argument
86 .addr = _addr, \
/drivers/net/wireless/ath/ath9k/
Dhw.h85 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ argument
86 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))

12