| /drivers/reset/sti/ |
| D | reset-stih407.c | 18 #define STIH407_PDN_0(_bit) \ argument
19 _SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
20 #define STIH407_PDN_1(_bit) \ argument
21 _SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
22 #define STIH407_PDN_ETH(_bit, _stat) \ argument
23 _SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat)
57 #define STIH407_SRST_CORE(_reg, _bit) \ argument
58 _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
60 #define STIH407_SRST_SBC(_reg, _bit) \ argument
61 _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
[all …]
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| /drivers/clk/meson/ |
| D | clk-regmap.h | 117 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ argument
121 .bit_idx = (_bit), \
132 #define MESON_PCLK(_name, _reg, _bit, _pname) \ argument
133 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname)
135 #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ argument
136 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname)
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| D | gxbb-aoclk.c | 24 #define GXBB_AO_GATE(_name, _bit) \ argument
28 .bit_idx = (_bit), \
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| D | axg-aoclk.c | 35 #define AXG_AO_GATE(_name, _bit) \ argument
39 .bit_idx = (_bit), \
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| D | g12a-aoclk.c | 44 #define AXG_AO_GATE(_name, _reg, _bit) \ argument
48 .bit_idx = (_bit), \
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| D | axg-audio.c | 23 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ argument
26 .bit_idx = (_bit), \
69 #define AUD_PCLK_GATE(_name, _reg, _bit) { \ argument
72 .bit_idx = (_bit), \
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| D | axg.c | 1100 #define MESON_GATE(_name, _reg, _bit) \ argument
1101 MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw)
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| /drivers/pinctrl/mediatek/ |
| D | pinctrl-mtk-common.h | 109 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ argument
113 .bit = _bit, \
157 #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ argument
161 .bit = _bit, \
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| D | pinctrl-mt2701.c | 31 #define MTK_PINMUX_SPEC(_pin, _offset, _bit) \ argument
35 .bit = _bit, \
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| /drivers/clk/bcm/ |
| D | clk-kona.h | 99 #define POLICY(_offset, _bit) \ argument
102 .bit = (_bit), \
383 #define TRIGGER(_offset, _bit) \ argument
386 .bit = (_bit), \
442 #define CCU_LVM_EN(_offset, _bit) \ argument
445 .bit = (_bit), \
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| /drivers/clk/mvebu/ |
| D | armada-37xx-periph.c | 129 #define PERIPH_GATE(_name, _bit) \ argument
132 .bit_idx = _bit, \
181 #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\ argument
182 static PERIPH_GATE(_name, _bit); \
186 #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \ argument
187 static PERIPH_GATE(_name, _bit); \
191 #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \ argument
192 static PERIPH_GATE(_name, _bit); \
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| /drivers/reset/ |
| D | reset-uniphier.c | 28 #define UNIPHIER_RESET(_id, _reg, _bit) \ argument
32 .bit = (_bit), \
35 #define UNIPHIER_RESETX(_id, _reg, _bit) \ argument
39 .bit = (_bit), \
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| /drivers/clk/uniphier/ |
| D | clk-uniphier.h | 95 #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \ argument
103 .bit = (_bit), \
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| /drivers/clk/zte/ |
| D | clk.h | 60 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ argument
64 .bit_idx = (_bit), \
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| /drivers/memory/tegra/ |
| D | tegra20.c | 170 #define TEGRA20_MC_RESET(_name, _control, _status, _reset, _bit) \ argument
177 .bit = _bit, \
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| D | tegra30.c | 984 #define TEGRA30_MC_RESET(_name, _control, _status, _bit) \ argument
990 .bit = _bit, \
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| D | tegra114.c | 940 #define TEGRA114_MC_RESET(_name, _control, _status, _bit) \ argument
946 .bit = _bit, \
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| D | tegra210.c | 1080 #define TEGRA210_MC_RESET(_name, _control, _status, _bit) \ argument
1086 .bit = _bit, \
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| D | tegra124.c | 971 #define TEGRA124_MC_RESET(_name, _control, _status, _bit) \ argument
977 .bit = _bit, \
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| /drivers/net/wireless/realtek/rtlwifi/rtl8192se/ |
| D | fw.h | 318 #define FW_CMD_IO_CLR(rtlpriv, _bit) \ argument
321 rtlpriv->rtlhal.fwcmd_iomap &= (~_bit); \
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| /drivers/clk/ |
| D | clk-oxnas.c | 89 #define OXNAS_GATE(_name, _bit, _parents) \ argument
91 .bit = (_bit), \
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| /drivers/staging/rtl8723bs/hal/ |
| D | odm_interface.h | 40 #define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit)
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| /drivers/iommu/amd/ |
| D | init.c | 923 int _bit = bit & 0x3f; in set_dev_entry_bit() local
925 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit); in set_dev_entry_bit()
931 int _bit = bit & 0x3f; in get_dev_entry_bit() local
933 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit; in get_dev_entry_bit()
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| /drivers/input/misc/ |
| D | uinput.c | 837 #define uinput_set_bit(_arg, _bit, _max) \ argument
844 else set_bit((_arg), udev->dev->_bit); \
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| /drivers/target/ |
| D | target_core_configfs.c | 2854 #define ALUA_SUPPORTED_STATE_ATTR(_name, _bit) \ argument
2860 !!(t->tg_pt_gp_alua_supported_states & _bit)); \
2887 t->tg_pt_gp_alua_supported_states |= _bit; \
2889 t->tg_pt_gp_alua_supported_states &= ~_bit; \
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