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Searched refs:a6xx_gmu (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/msm/adreno/
Da6xx_gmu.h44 struct a6xx_gmu { struct
90 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset) in gmu_read() argument
95 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value) in gmu_write()
101 gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size) in gmu_write_bulk()
107 static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or) in gmu_rmw()
116 static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi) in gmu_read64()
130 static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset) in gmu_read_rscc()
135 static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value) in gmu_write_rscc()
202 void a6xx_hfi_init(struct a6xx_gmu *gmu);
203 int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);
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Da6xx_gmu.c17 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) in a6xx_gmu_fault()
37 struct a6xx_gmu *gmu = data; in a6xx_gmu_irq()
61 struct a6xx_gmu *gmu = data; in a6xx_hfi_irq()
76 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu) in a6xx_gmu_sptprac_is_on()
92 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) in a6xx_gmu_gx_is_on()
111 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_gmu_set_freq()
171 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_gmu_get_freq()
176 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) in a6xx_gmu_check_idle_level()
197 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu) in a6xx_gmu_wait_for_idle()
202 static int a6xx_gmu_start(struct a6xx_gmu *gmu) in a6xx_gmu_start()
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Da6xx_hfi.c26 static int a6xx_hfi_queue_read(struct a6xx_gmu *gmu, in a6xx_hfi_queue_read()
62 static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu, in a6xx_hfi_queue_write()
96 static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, u32 id, u32 seqnum, in a6xx_hfi_wait_for_ack()
165 static int a6xx_hfi_send_msg(struct a6xx_gmu *gmu, int id, in a6xx_hfi_send_msg()
188 static int a6xx_hfi_send_gmu_init(struct a6xx_gmu *gmu, int boot_state) in a6xx_hfi_send_gmu_init()
200 static int a6xx_hfi_get_fw_version(struct a6xx_gmu *gmu, u32 *version) in a6xx_hfi_get_fw_version()
211 static int a6xx_hfi_send_perf_table_v1(struct a6xx_gmu *gmu) in a6xx_hfi_send_perf_table_v1()
233 static int a6xx_hfi_send_perf_table(struct a6xx_gmu *gmu) in a6xx_hfi_send_perf_table()
392 static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) in a6xx_hfi_send_bw_table()
411 static int a6xx_hfi_send_test(struct a6xx_gmu *gmu) in a6xx_hfi_send_test()
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Da6xx_gpu.h33 struct a6xx_gmu gmu;
75 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);
77 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);
79 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
80 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
Da6xx_gpu.c431 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_set_hwcg()
Da6xx_gpu_state.c744 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in _a6xx_get_gmu_registers()
/drivers/gpu/drm/msm/
DMakefile17 adreno/a6xx_gmu.o \