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Searched refs:acr (Results 1 – 25 of 43) sorted by relevance

12

/drivers/gpu/drm/nouveau/nvkm/subdev/acr/
Dbase.c29 nvkm_acr_hsf_find(struct nvkm_acr *acr, const char *name) in nvkm_acr_hsf_find() argument
32 list_for_each_entry(hsf, &acr->hsf, head) { in nvkm_acr_hsf_find()
40 nvkm_acr_hsf_boot(struct nvkm_acr *acr, const char *name) in nvkm_acr_hsf_boot() argument
42 struct nvkm_subdev *subdev = &acr->subdev; in nvkm_acr_hsf_boot()
46 hsf = nvkm_acr_hsf_find(acr, name); in nvkm_acr_hsf_boot()
55 ret = hsf->func->boot(acr, hsf); in nvkm_acr_hsf_boot()
67 nvkm_acr_unload(struct nvkm_acr *acr) in nvkm_acr_unload() argument
69 if (acr->done) { in nvkm_acr_unload()
70 nvkm_acr_hsf_boot(acr, "unload"); in nvkm_acr_unload()
71 acr->done = false; in nvkm_acr_unload()
[all …]
Dgp102.c33 gp102_acr_wpr_patch(struct nvkm_acr *acr, s64 adjust) in gp102_acr_wpr_patch() argument
41 nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr)); in gp102_acr_wpr_patch()
42 wpr_header_v1_dump(&acr->subdev, &hdr); in gp102_acr_wpr_patch()
44 list_for_each_entry(lsfw, &acr->lsfw, head) { in gp102_acr_wpr_patch()
48 nvkm_robj(acr->wpr, hdr.lsb_offset, &lsb, sizeof(lsb)); in gp102_acr_wpr_patch()
49 lsb_header_v1_dump(&acr->subdev, &lsb); in gp102_acr_wpr_patch()
51 lsfw->func->bld_patch(acr, lsb.tail.bl_data_off, adjust); in gp102_acr_wpr_patch()
60 gp102_acr_wpr_build_lsb(struct nvkm_acr *acr, struct nvkm_acr_lsfw *lsfw) in gp102_acr_wpr_build_lsb() argument
70 nvkm_wobj(acr->wpr, lsfw->offset.lsb, &hdr, sizeof(hdr)); in gp102_acr_wpr_build_lsb()
75 gp102_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos) in gp102_acr_wpr_build() argument
[all …]
Dgm200.c40 gm200_acr_nofw(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif) in gm200_acr_nofw() argument
42 nvkm_warn(&acr->subdev, "firmware unavailable\n"); in gm200_acr_nofw()
47 gm200_acr_init(struct nvkm_acr *acr) in gm200_acr_init() argument
49 return nvkm_acr_hsf_boot(acr, "load"); in gm200_acr_init()
53 gm200_acr_wpr_check(struct nvkm_acr *acr, u64 *start, u64 *limit) in gm200_acr_wpr_check() argument
55 struct nvkm_device *device = acr->subdev.device; in gm200_acr_wpr_check()
65 gm200_acr_wpr_patch(struct nvkm_acr *acr, s64 adjust) in gm200_acr_wpr_patch() argument
67 struct nvkm_subdev *subdev = &acr->subdev; in gm200_acr_wpr_patch()
74 nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr)); in gm200_acr_wpr_patch()
77 list_for_each_entry(lsfw, &acr->lsfw, head) { in gm200_acr_wpr_patch()
[all …]
Dgm20b.c33 gm20b_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size) in gm20b_acr_wpr_alloc() argument
35 struct nvkm_subdev *subdev = &acr->subdev; in gm20b_acr_wpr_alloc()
37 acr->func->wpr_check(acr, &acr->wpr_start, &acr->wpr_end); in gm20b_acr_wpr_alloc()
39 if ((acr->wpr_end - acr->wpr_start) < wpr_size) { in gm20b_acr_wpr_alloc()
45 wpr_size, 0, true, &acr->wpr); in gm20b_acr_wpr_alloc()
49 gm20b_acr_load_bld(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf) in gm20b_acr_load_bld() argument
63 flcn_bl_dmem_desc_dump(&acr->subdev, &hsdesc); in gm20b_acr_load_bld()
69 gm20b_acr_load_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw) in gm20b_acr_load_load() argument
73 desc->ucode_blob_base = nvkm_memory_addr(acr->wpr); in gm20b_acr_load_load()
74 desc->ucode_blob_size = nvkm_memory_size(acr->wpr); in gm20b_acr_load_load()
[all …]
Dtu102.c33 tu102_acr_init(struct nvkm_acr *acr) in tu102_acr_init() argument
35 int ret = nvkm_acr_hsf_boot(acr, "AHESASC"); in tu102_acr_init()
39 return nvkm_acr_hsf_boot(acr, "ASB"); in tu102_acr_init()
43 tu102_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos) in tu102_acr_wpr_build() argument
50 nvkm_wo32(acr->wpr, 0x200, 0xffffffff); in tu102_acr_wpr_build()
53 list_for_each_entry(lsfw, &acr->lsfw, head) { in tu102_acr_wpr_build()
65 nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr)); in tu102_acr_wpr_build()
69 ret = gp102_acr_wpr_build_lsb(acr, lsfw); in tu102_acr_wpr_build()
74 nvkm_wobj(acr->wpr, lsfw->offset.img, in tu102_acr_wpr_build()
79 lsfw->func->bld_write(acr, lsfw->offset.bld, lsfw); in tu102_acr_wpr_build()
[all …]
DKbuild2 nvkm-y += nvkm/subdev/acr/base.o
3 nvkm-y += nvkm/subdev/acr/hsfw.o
4 nvkm-y += nvkm/subdev/acr/lsfw.o
5 nvkm-y += nvkm/subdev/acr/gm200.o
6 nvkm-y += nvkm/subdev/acr/gm20b.o
7 nvkm-y += nvkm/subdev/acr/gp102.o
8 nvkm-y += nvkm/subdev/acr/gp108.o
9 nvkm-y += nvkm/subdev/acr/gp10b.o
10 nvkm-y += nvkm/subdev/acr/tu102.o
Dlsfw.c38 nvkm_acr_lsfw_del_all(struct nvkm_acr *acr) in nvkm_acr_lsfw_del_all() argument
41 list_for_each_entry_safe(lsfw, lsft, &acr->lsfw, head) { in nvkm_acr_lsfw_del_all()
47 nvkm_acr_lsfw_get(struct nvkm_acr *acr, enum nvkm_acr_lsf_id id) in nvkm_acr_lsfw_get() argument
50 list_for_each_entry(lsfw, &acr->lsfw, head) { in nvkm_acr_lsfw_get()
58 nvkm_acr_lsfw_add(const struct nvkm_acr_lsf_func *func, struct nvkm_acr *acr, in nvkm_acr_lsfw_add() argument
63 if (!acr || list_empty(&acr->hsfw)) in nvkm_acr_lsfw_add()
66 lsfw = nvkm_acr_lsfw_get(acr, id); in nvkm_acr_lsfw_add()
68 nvkm_error(&acr->subdev, "LSFW %d redefined\n", id); in nvkm_acr_lsfw_add()
77 list_add_tail(&lsfw->head, &acr->lsfw); in nvkm_acr_lsfw_add()
93 struct nvkm_acr *acr = subdev->device->acr; in nvkm_acr_lsfw_load_sig_image_desc_() local
[all …]
Dhsfw.c41 nvkm_acr_hsfw_del_all(struct nvkm_acr *acr) in nvkm_acr_hsfw_del_all() argument
44 list_for_each_entry_safe(hsfw, hsft, &acr->hsfw, head) { in nvkm_acr_hsfw_del_all()
50 nvkm_acr_hsfw_load_image(struct nvkm_acr *acr, const char *name, int ver, in nvkm_acr_hsfw_load_image() argument
53 struct nvkm_subdev *subdev = &acr->subdev; in nvkm_acr_hsfw_load_image()
125 nvkm_acr_hsfw_load_bl(struct nvkm_acr *acr, const char *name, int ver, in nvkm_acr_hsfw_load_bl() argument
128 struct nvkm_subdev *subdev = &acr->subdev; in nvkm_acr_hsfw_load_bl()
154 nvkm_acr_hsfw_load(struct nvkm_acr *acr, const char *bl, const char *fw, in nvkm_acr_hsfw_load() argument
166 list_add_tail(&hsfw->head, &acr->hsfw); in nvkm_acr_hsfw_load()
168 ret = nvkm_acr_hsfw_load_bl(acr, bl, version, hsfw); in nvkm_acr_hsfw_load()
172 ret = nvkm_acr_hsfw_load_image(acr, fw, version, hsfw); in nvkm_acr_hsfw_load()
Dgp108.c29 gp108_acr_hsfw_bld(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf) in gp108_acr_hsfw_bld() argument
45 flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hsdesc); in gp108_acr_hsfw_bld()
/drivers/gpu/drm/nouveau/nvkm/engine/sec2/
Dgp102.c88 gp102_sec2_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) in gp102_sec2_acr_bld_patch() argument
91 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); in gp102_sec2_acr_bld_patch()
95 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); in gp102_sec2_acr_bld_patch()
96 loader_config_v1_dump(&acr->subdev, &hdr); in gp102_sec2_acr_bld_patch()
100 gp102_sec2_acr_bld_write(struct nvkm_acr *acr, u32 bld, in gp102_sec2_acr_bld_write() argument
117 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); in gp102_sec2_acr_bld_write()
272 gp102_sec2_acr_bld_patch_1(struct nvkm_acr *acr, u32 bld, s64 adjust) in gp102_sec2_acr_bld_patch_1() argument
275 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); in gp102_sec2_acr_bld_patch_1()
278 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); in gp102_sec2_acr_bld_patch_1()
279 flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hdr); in gp102_sec2_acr_bld_patch_1()
[all …]
Dpriv.h20 const struct nvkm_acr_lsf_func *acr; member
/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dgp108.c29 gp108_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) in gp108_gr_acr_bld_patch() argument
32 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); in gp108_gr_acr_bld_patch()
35 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); in gp108_gr_acr_bld_patch()
36 flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hdr); in gp108_gr_acr_bld_patch()
40 gp108_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld, in gp108_gr_acr_bld_write() argument
56 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); in gp108_gr_acr_bld_write()
Dgm20b.c34 gm20b_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) in gm20b_gr_acr_bld_patch() argument
39 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm20b_gr_acr_bld_patch()
46 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm20b_gr_acr_bld_patch()
48 flcn_bl_dmem_desc_dump(&acr->subdev, &hdr); in gm20b_gr_acr_bld_patch()
52 gm20b_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld, in gm20b_gr_acr_bld_write() argument
70 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm20b_gr_acr_bld_write()
87 if (!device->acr) { in gm20b_gr_init_gpc_mmu()
Dgm200.c47 gm200_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) in gm200_gr_acr_bld_patch() argument
50 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm200_gr_acr_bld_patch()
53 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm200_gr_acr_bld_patch()
54 flcn_bl_dmem_desc_v1_dump(&acr->subdev, &hdr); in gm200_gr_acr_bld_patch()
58 gm200_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld, in gm200_gr_acr_bld_write() argument
74 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm200_gr_acr_bld_write()
/drivers/gpu/drm/radeon/
Ddce3_1_afmt.c171 const struct radeon_hdmi_acr *acr) in dce3_2_hdmi_update_acr() argument
181 HDMI0_ACR_CTS_32(acr->cts_32khz), in dce3_2_hdmi_update_acr()
184 HDMI0_ACR_N_32(acr->n_32khz), in dce3_2_hdmi_update_acr()
188 HDMI0_ACR_CTS_44(acr->cts_44_1khz), in dce3_2_hdmi_update_acr()
191 HDMI0_ACR_N_44(acr->n_44_1khz), in dce3_2_hdmi_update_acr()
195 HDMI0_ACR_CTS_48(acr->cts_48khz), in dce3_2_hdmi_update_acr()
198 HDMI0_ACR_N_48(acr->n_48khz), in dce3_2_hdmi_update_acr()
Dr600_hdmi.c178 const struct radeon_hdmi_acr *acr) in r600_hdmi_update_acr() argument
193 HDMI0_ACR_CTS_32(acr->cts_32khz), in r600_hdmi_update_acr()
196 HDMI0_ACR_N_32(acr->n_32khz), in r600_hdmi_update_acr()
200 HDMI0_ACR_CTS_44(acr->cts_44_1khz), in r600_hdmi_update_acr()
203 HDMI0_ACR_N_44(acr->n_44_1khz), in r600_hdmi_update_acr()
207 HDMI0_ACR_CTS_48(acr->cts_48khz), in r600_hdmi_update_acr()
210 HDMI0_ACR_N_48(acr->n_48khz), in r600_hdmi_update_acr()
Devergreen_hdmi.c68 const struct radeon_hdmi_acr *acr) in evergreen_hdmi_update_acr() argument
87 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); in evergreen_hdmi_update_acr()
88 WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz); in evergreen_hdmi_update_acr()
90 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); in evergreen_hdmi_update_acr()
91 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); in evergreen_hdmi_update_acr()
93 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); in evergreen_hdmi_update_acr()
94 WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz); in evergreen_hdmi_update_acr()
Dradeon_audio.c83 const struct radeon_hdmi_acr *acr);
85 const struct radeon_hdmi_acr *acr);
87 const struct radeon_hdmi_acr *acr);
624 const struct radeon_hdmi_acr *acr = radeon_audio_acr(clock); in radeon_audio_update_acr() local
632 radeon_encoder->audio->update_acr(encoder, dig->afmt->offset, acr); in radeon_audio_update_acr()
/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
Dgm20b.c76 gm20b_pmu_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) in gm20b_pmu_acr_bld_patch() argument
81 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm20b_pmu_acr_bld_patch()
91 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm20b_pmu_acr_bld_patch()
93 loader_config_dump(&acr->subdev, &hdr); in gm20b_pmu_acr_bld_patch()
97 gm20b_pmu_acr_bld_write(struct nvkm_acr *acr, u32 bld, in gm20b_pmu_acr_bld_write() argument
119 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); in gm20b_pmu_acr_bld_write()
233 ver, fwif->acr); in gm20b_pmu_load()
/drivers/tty/serial/
Dsunsu.c86 unsigned char acr; member
176 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
179 serial_icr_write(up, UART_ACR, up->acr);
273 up->acr |= UART_ACR_TXDIS; in sunsu_stop_tx()
274 serial_icr_write(up, UART_ACR, up->acr); in sunsu_stop_tx()
291 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { in sunsu_start_tx()
292 up->acr &= ~UART_ACR_TXDIS; in sunsu_start_tx()
293 serial_icr_write(up, UART_ACR, up->acr); in sunsu_start_tx()
624 up->acr = 0; in sunsu_startup()
/drivers/gpu/drm/nouveau/nvkm/engine/device/
Dbase.c2032 .acr = gm200_acr_new,
2070 .acr = gm200_acr_new,
2108 .acr = gm200_acr_new,
2145 .acr = gm20b_acr_new,
2170 .acr = gm200_acr_new,
2210 .acr = gp102_acr_new,
2248 .acr = gp102_acr_new,
2286 .acr = gp102_acr_new,
2323 .acr = gp102_acr_new,
2361 .acr = gp108_acr_new,
[all …]
/drivers/gpu/drm/nouveau/nvkm/nvfw/
DKbuild6 nvkm-y += nvkm/nvfw/acr.o
/drivers/power/supply/
Dds2760_battery.c376 unsigned char acr[2]; in ds2760_battery_set_current_accum() local
382 acr[0] = acr_val >> 8; in ds2760_battery_set_current_accum()
383 acr[1] = acr_val & 0xff; in ds2760_battery_set_current_accum()
385 if (w1_ds2760_write(di->dev, acr, DS2760_CURRENT_ACCUM_MSB, 2) < 2) in ds2760_battery_set_current_accum()
/drivers/gpu/drm/nouveau/include/nvkm/subdev/
Dsecboot.h45 struct nvkm_acr *acr; member
/drivers/tty/serial/8250/
D8250.h136 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); in serial_icr_read()
139 serial_icr_write(up, UART_ACR, up->acr); in serial_icr_read()

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