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Searched refs:alpha_en (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dpp.c105 uint32_t alpha_en = 1; in dpp2_cnv_setup() local
133 alpha_en = 0; in dpp2_cnv_setup()
184 alpha_en = 0; in dpp2_cnv_setup()
188 alpha_en = 0; in dpp2_cnv_setup()
204 alpha_en = 0; in dpp2_cnv_setup()
208 alpha_en = 0; in dpp2_cnv_setup()
223 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp2_cnv_setup()
314 if (scl_data->lb_params.alpha_en in dscl2_calc_lb_num_partitions()
Ddcn20_hwseq.c1451 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; in dcn20_update_dchubp_dpp()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp.c290 uint32_t alpha_en; in dpp1_cnv_setup() local
301 alpha_en = 1; in dpp1_cnv_setup()
336 alpha_en = 0; in dpp1_cnv_setup()
388 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp1_cnv_setup()
Ddcn10_dpp_dscl.c219 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ in dpp1_dscl_set_lb()
225 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ in dpp1_dscl_set_lb()
457 if (scl_data->lb_params.alpha_en in dpp1_dscl_calc_lb_num_partitions()
Ddcn10_hw_sequencer.c2461 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha; in update_scaler()
2871 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; in dcn10_disconnect_pipes()
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dtransform.h154 bool alpha_en; member
/drivers/gpu/drm/rockchip/
Drockchip_vop_reg.c269 .alpha_en = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 0),
285 .alpha_en = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 0),
302 .alpha_en = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 0),
Drockchip_drm_vop.h183 struct vop_reg alpha_en; member
Drockchip_drm_vop.c1021 VOP_WIN_SET(vop, win, alpha_en, 1); in vop_plane_atomic_update()
1024 VOP_WIN_SET(vop, win, alpha_en, 0); in vop_plane_atomic_update()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dpp.c181 uint32_t alpha_en = 1; in dpp3_cnv_setup() local
212 alpha_en = 0; in dpp3_cnv_setup()
307 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); in dpp3_cnv_setup()
/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_hw_sequencer.c312 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; in dce60_program_front_end_for_pipe()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_transform.c486 REG_UPDATE(LB_DATA_FORMAT, ALPHA_EN, data->lb_params.alpha_en); in dce_transform_set_scaler()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c1494 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; in apply_single_controller_ctx_to_hw()
2583 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; in dce110_program_front_end_for_pipe()
/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c1163 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha; in resource_build_scaling_params()