Home
last modified time | relevance | path

Searched refs:asic_type (Results 1 – 25 of 101) sorted by relevance

12345

/drivers/misc/habanalabs/common/
Dhabanalabs_drv.c63 enum hl_asic_type asic_type; in get_asic_type() local
67 asic_type = ASIC_GOYA; in get_asic_type()
70 asic_type = ASIC_GAUDI; in get_asic_type()
73 asic_type = ASIC_INVALID; in get_asic_type()
77 return asic_type; in get_asic_type()
259 enum hl_asic_type asic_type, int minor) in create_hdev() argument
274 hdev->asic_type = get_asic_type(pdev->device); in create_hdev()
275 if (hdev->asic_type == ASIC_INVALID) { in create_hdev()
281 hdev->asic_type = asic_type; in create_hdev()
Dmmu.c297 switch (hdev->asic_type) { in hl_mmu_if_set_funcs()
304 hdev->asic_type); in hl_mmu_if_set_funcs()
/drivers/gpu/drm/amd/amdgpu/
Dumc_v6_1.c99 if (adev->asic_type == CHIP_ARCTURUS) { in umc_v6_1_clear_error_count_per_channel()
177 if (adev->asic_type == CHIP_ARCTURUS) { in umc_v6_1_query_correctable_error_count()
232 if (adev->asic_type == CHIP_ARCTURUS) { in umc_v6_1_querry_uncorrectable_error_count()
267 if ((adev->asic_type == CHIP_ARCTURUS) && in umc_v6_1_query_ras_error_count()
284 if ((adev->asic_type == CHIP_ARCTURUS) && in umc_v6_1_query_ras_error_count()
305 if (adev->asic_type == CHIP_ARCTURUS) { in umc_v6_1_query_error_address()
382 if ((adev->asic_type == CHIP_ARCTURUS) && in umc_v6_1_query_ras_error_address()
398 if ((adev->asic_type == CHIP_ARCTURUS) && in umc_v6_1_query_ras_error_address()
412 if (adev->asic_type == CHIP_ARCTURUS) { in umc_v6_1_err_cnt_init_per_channel()
Dsoc15.c249 if (adev->asic_type == CHIP_RENOIR) in soc15_get_xclk()
251 if (adev->asic_type == CHIP_RAVEN) in soc15_get_xclk()
300 switch (adev->asic_type) { in soc15_read_bios_from_rom()
512 switch (adev->asic_type) { in soc15_asic_reset_method()
564 switch (adev->asic_type) { in soc15_supports_baco()
657 switch (adev->asic_type) { in soc15_reg_base_init()
682 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); in soc15_reg_base_init()
703 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) in soc15_set_ip_blocks()
709 } else if (adev->asic_type == CHIP_VEGA20 || in soc15_set_ip_blocks()
710 adev->asic_type == CHIP_ARCTURUS) { in soc15_set_ip_blocks()
[all …]
Dgmc_v9_0.c426 if (adev->asic_type >= CHIP_VEGA20) in gmc_v9_0_ecc_interrupt_state()
587 switch (adev->asic_type) { in gmc_v9_0_process_interrupt()
730 adev->asic_type == CHIP_VEGA20) { in gmc_v9_0_flush_gpu_tlb()
857 adev->asic_type == CHIP_VEGA20); in gmc_v9_0_flush_gpu_tlb_pasid()
1072 if (adev->asic_type == CHIP_ARCTURUS && in gmc_v9_0_get_vm_pte()
1088 switch (adev->asic_type) { in gmc_v9_0_get_vbios_fb_size()
1131 switch (adev->asic_type) { in gmc_v9_0_set_umc_funcs()
1158 switch (adev->asic_type) { in gmc_v9_0_set_mmhub_funcs()
1170 switch (adev->asic_type) { in gmc_v9_0_set_gfxhub_funcs()
1216 if (!amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) { in gmc_v9_0_late_init()
[all …]
Dnavi10_ih.c63 if (adev->asic_type < CHIP_SIENNA_CICHLID) in force_update_wptr_for_self_int()
97 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { in navi10_ih_enable_interrupts()
112 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { in navi10_ih_enable_interrupts()
128 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { in navi10_ih_enable_interrupts()
154 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { in navi10_ih_disable_interrupts()
173 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { in navi10_ih_disable_interrupts()
193 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { in navi10_ih_disable_interrupts()
301 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { in navi10_ih_irq_init()
314 switch (adev->asic_type) { in navi10_ih_irq_init()
360 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { in navi10_ih_irq_init()
[all …]
Dvce_v3_0.c305 if (adev->asic_type >= CHIP_STONEY) in vce_v3_0_start()
342 if (adev->asic_type >= CHIP_STONEY) in vce_v3_0_stop()
368 if ((adev->asic_type == CHIP_FIJI) || in vce_v3_0_get_harvest_config()
369 (adev->asic_type == CHIP_STONEY)) in vce_v3_0_get_harvest_config()
389 if ((adev->asic_type == CHIP_POLARIS10) || in vce_v3_0_get_harvest_config()
390 (adev->asic_type == CHIP_POLARIS11) || in vce_v3_0_get_harvest_config()
391 (adev->asic_type == CHIP_POLARIS12) || in vce_v3_0_get_harvest_config()
392 (adev->asic_type == CHIP_VEGAM)) in vce_v3_0_get_harvest_config()
541 if (adev->asic_type >= CHIP_STONEY) { in vce_v3_0_mc_resume()
948 if (adev->asic_type >= CHIP_STONEY) { in vce_v3_0_set_ring_funcs()
Dgmc_v10_0.c618 switch (adev->asic_type) { in gmc_v10_0_set_umc_funcs()
640 switch (adev->asic_type) { in gmc_v10_0_set_gfxhub_funcs()
744 switch (adev->asic_type) { in gmc_v10_0_mc_init()
794 if (adev->asic_type == CHIP_SIENNA_CICHLID && amdgpu_emu_mode == 1) { in gmc_v10_0_sw_init()
806 switch (adev->asic_type) { in gmc_v10_0_sw_init()
919 switch (adev->asic_type) { in gmc_v10_0_init_golden_registers()
1086 if (adev->asic_type == CHIP_SIENNA_CICHLID || in gmc_v10_0_set_clockgating_state()
1087 adev->asic_type == CHIP_NAVY_FLOUNDER) in gmc_v10_0_set_clockgating_state()
1099 if (adev->asic_type == CHIP_SIENNA_CICHLID || in gmc_v10_0_get_clockgating_state()
1100 adev->asic_type == CHIP_NAVY_FLOUNDER) in gmc_v10_0_get_clockgating_state()
Dmmhub_v2_0.c131 switch (adev->asic_type) { in mmhub_v2_0_print_l2_protection_fault_status()
543 switch (adev->asic_type) { in mmhub_v2_0_update_medium_grain_clock_gating()
576 switch (adev->asic_type) { in mmhub_v2_0_update_medium_grain_clock_gating()
598 switch (adev->asic_type) { in mmhub_v2_0_update_medium_grain_light_sleep()
614 switch (adev->asic_type) { in mmhub_v2_0_update_medium_grain_light_sleep()
632 switch (adev->asic_type) { in mmhub_v2_0_set_clockgating()
657 switch (adev->asic_type) { in mmhub_v2_0_get_clockgating()
Damdgpu_acp.c258 switch (adev->asic_type) { in acp_hw_init()
270 switch (adev->asic_type) { in acp_hw_init()
287 switch (adev->asic_type) { in acp_hw_init()
328 adev->acp.acp_cell[0].platform_data = &adev->asic_type; in acp_hw_init()
329 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type); in acp_hw_init()
Damdgpu_gmc.c76 if (adev->asic_type >= CHIP_VEGA10) { in amdgpu_gmc_pd_addr()
390 switch (adev->asic_type) { in amdgpu_gmc_tmz_set()
427 switch (adev->asic_type) { in amdgpu_gmc_noretry_set()
486 switch (adev->asic_type) { in amdgpu_gmc_get_vbios_allocations()
Dpsp_v11_0.c86 switch (adev->asic_type) { in psp_v11_0_init_microcode()
116 if (adev->asic_type != CHIP_SIENNA_CICHLID && in psp_v11_0_init_microcode()
117 adev->asic_type != CHIP_NAVY_FLOUNDER) { in psp_v11_0_init_microcode()
123 switch (adev->asic_type) { in psp_v11_0_init_microcode()
410 (adev->asic_type != CHIP_SIENNA_CICHLID) && in psp_v11_0_ring_init()
411 (adev->asic_type != CHIP_NAVY_FLOUNDER)) in psp_v11_0_ring_init()
Dsdma_v4_0.c453 switch (adev->asic_type) { in sdma_v4_0_init_golden_registers()
517 switch (adev->asic_type) { in sdma_v4_0_setup_ulv()
568 if (adev->asic_type == CHIP_ARCTURUS) in sdma_v4_0_destroy_inst_ctx()
601 switch (adev->asic_type) { in sdma_v4_0_init_microcode()
643 if (adev->asic_type == CHIP_ARCTURUS) { in sdma_v4_0_init_microcode()
1079 if (adev->asic_type == CHIP_ARCTURUS && in sdma_v4_0_ctx_switch_enable()
1364 switch (adev->asic_type) { in sdma_v4_0_init_pg()
1805 switch (adev->asic_type) { in sdma_v4_0_fw_support_paging_queue()
1825 else if (adev->asic_type == CHIP_ARCTURUS) in sdma_v4_0_early_init()
1837 if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev))) in sdma_v4_0_early_init()
[all …]
Dmmhub_v1_0.c456 if (adev->asic_type != CHIP_RAVEN) { in mmhub_v1_0_update_medium_grain_clock_gating()
472 if (adev->asic_type != CHIP_RAVEN) in mmhub_v1_0_update_medium_grain_clock_gating()
489 if (adev->asic_type != CHIP_RAVEN) in mmhub_v1_0_update_medium_grain_clock_gating()
502 if (adev->asic_type != CHIP_RAVEN) in mmhub_v1_0_update_medium_grain_clock_gating()
508 if (adev->asic_type != CHIP_RAVEN && def2 != data2) in mmhub_v1_0_update_medium_grain_clock_gating()
534 switch (adev->asic_type) { in mmhub_v1_0_set_clockgating()
Damdgpu_uvd.c147 switch (adev->asic_type) { in amdgpu_uvd_sw_init()
238 if (adev->asic_type < CHIP_VEGA20) { in amdgpu_uvd_sw_init()
259 if ((adev->asic_type == CHIP_POLARIS10 || in amdgpu_uvd_sw_init()
260 adev->asic_type == CHIP_POLARIS11) && in amdgpu_uvd_sw_init()
304 switch (adev->asic_type) { in amdgpu_uvd_sw_init()
318 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; in amdgpu_uvd_sw_init()
384 if (adev->asic_type < CHIP_POLARIS10) { in amdgpu_uvd_suspend()
1090 if (adev->asic_type >= CHIP_VEGA10) { in amdgpu_uvd_send_msg()
Dgfx_v8_0.c734 switch (adev->asic_type) { in gfx_v8_0_init_golden_registers()
942 if ((adev->asic_type != CHIP_STONEY) && in gfx_v8_0_free_microcode()
943 (adev->asic_type != CHIP_TOPAZ)) in gfx_v8_0_free_microcode()
963 switch (adev->asic_type) { in gfx_v8_0_init_microcode()
995 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { in gfx_v8_0_init_microcode()
1015 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { in gfx_v8_0_init_microcode()
1036 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { in gfx_v8_0_init_microcode()
1116 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { in gfx_v8_0_init_microcode()
1136 if ((adev->asic_type != CHIP_STONEY) && in gfx_v8_0_init_microcode()
1137 (adev->asic_type != CHIP_TOPAZ)) { in gfx_v8_0_init_microcode()
[all …]
Dgmc_v8_0.c131 switch (adev->asic_type) { in gmc_v8_0_init_golden_registers()
228 switch (adev->asic_type) { in gmc_v8_0_init_microcode()
606 switch (adev->asic_type) { in gmc_v8_0_mc_init()
1122 if ((adev->asic_type == CHIP_FIJI) || in gmc_v8_0_sw_init()
1123 (adev->asic_type == CHIP_VEGAM)) in gmc_v8_0_sw_init()
1232 if (adev->asic_type == CHIP_TONGA) { in gmc_v8_0_hw_init()
1238 } else if (adev->asic_type == CHIP_POLARIS11 || in gmc_v8_0_hw_init()
1239 adev->asic_type == CHIP_POLARIS10 || in gmc_v8_0_hw_init()
1240 adev->asic_type == CHIP_POLARIS12) { in gmc_v8_0_hw_init()
1682 switch (adev->asic_type) { in gmc_v8_0_set_clockgating_state()
Ddf_v3_6.c276 if (adev->asic_type != CHIP_ARCTURUS) in df_v3_6_query_hashes()
582 switch (adev->asic_type) { in df_v3_6_pmc_start()
623 switch (adev->asic_type) { in df_v3_6_pmc_stop()
657 switch (adev->asic_type) { in df_v3_6_pmc_get_count()
Damdgpu_device.c925 if (adev->asic_type < CHIP_BONAIRE) { in amdgpu_device_doorbell_init()
953 if (adev->asic_type >= CHIP_VEGA10) in amdgpu_device_doorbell_init()
1128 if (adev->asic_type >= CHIP_BONAIRE) in amdgpu_device_resize_fb_bar()
1178 if (adev->asic_type == CHIP_FIJI) { in amdgpu_device_need_post()
1199 if (adev->asic_type >= CHIP_BONAIRE) in amdgpu_device_need_post()
1761 if (adev->asic_type != CHIP_NAVI12) in amdgpu_device_parse_gpu_info_fw()
1765 switch (adev->asic_type) { in amdgpu_device_parse_gpu_info_fw()
1857 if (adev->asic_type == CHIP_NAVI12) in amdgpu_device_parse_gpu_info_fw()
1933 switch (adev->asic_type) { in amdgpu_device_ip_early_init()
2120 if (adev->asic_type >= CHIP_VEGA10) { in amdgpu_device_fw_loading()
[all …]
Dvi.c283 switch (adev->asic_type) { in vi_init_golden_registers()
333 switch (adev->asic_type) { in vi_get_xclk()
702 switch (adev->asic_type) { in vi_asic_supports_baco()
728 switch (adev->asic_type) { in vi_asic_reset_method()
984 switch (adev->asic_type) { in vi_need_full_reset()
1132 switch (adev->asic_type) { in vi_common_early_init()
1627 switch (adev->asic_type) { in vi_common_set_clockgating_state()
1730 switch (adev->asic_type) { in vi_set_ip_blocks()
Dnv.c330 switch (adev->asic_type) { in nv_asic_reset_method()
432 switch (adev->asic_type) { in nv_reg_base_init()
475 if (adev->asic_type == CHIP_SIENNA_CICHLID) in nv_set_ip_blocks()
483 switch (adev->asic_type) { in nv_set_ip_blocks()
723 switch (adev->asic_type) { in nv_common_early_init()
1059 switch (adev->asic_type) { in nv_common_set_clockgating_state()
Dgfx_v9_0.c942 switch (adev->asic_type) { in gfx_v9_0_init_golden_registers()
993 if (adev->asic_type != CHIP_ARCTURUS) in gfx_v9_0_init_golden_registers()
1177 if ((adev->asic_type != CHIP_ARCTURUS) && in gfx_v9_0_check_fw_write_wait()
1184 switch (adev->asic_type) { in gfx_v9_0_check_fw_write_wait()
1283 if ((adev->asic_type == CHIP_RENOIR) && in check_if_enlarge_doorbell_range()
1296 switch (adev->asic_type) { in gfx_v9_0_check_if_need_gfxoff()
1601 if (adev->asic_type != CHIP_ARCTURUS && in gfx_v9_0_init_cp_compute_microcode()
1602 adev->asic_type != CHIP_RENOIR) { in gfx_v9_0_init_cp_compute_microcode()
1635 switch (adev->asic_type) { in gfx_v9_0_init_microcode()
1667 if (adev->asic_type != CHIP_ARCTURUS) { in gfx_v9_0_init_microcode()
[all …]
/drivers/gpu/drm/amd/amdkfd/
Dkfd_device.c534 struct pci_dev *pdev, unsigned int asic_type, bool vf) in kgd2kfd_probe() argument
540 if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2) in kgd2kfd_probe()
541 || asic_type >= sizeof(kfd2kgd_funcs) / sizeof(void *)) { in kgd2kfd_probe()
542 dev_err(kfd_device, "asic_type %d out of range\n", asic_type); in kgd2kfd_probe()
546 device_info = kfd_supported_devices[asic_type][vf]; in kgd2kfd_probe()
547 f2g = kfd2kgd_funcs[asic_type]; in kgd2kfd_probe()
551 amdgpu_asic_name[asic_type], vf ? "VF" : ""); in kgd2kfd_probe()
/drivers/gpu/drm/amd/pm/powerplay/
Dkv_dpm.c774 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_unforce_levels()
1381 if (adev->asic_type == CHIP_MULLINS) in kv_dpm_disable()
1743 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_dpm_powergate_acp()
1924 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { in kv_dpm_set_power_state()
1950 if (adev->asic_type == CHIP_MULLINS) in kv_dpm_set_power_state()
2004 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2109 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_force_dpm_highest()
2129 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_force_dpm_lowest()
2285 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { in kv_apply_state_adjust_rules()
2346 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { in kv_calculate_nbps_level_settings()
[all …]
/drivers/gpu/drm/amd/pm/
Damdgpu_pm.c352 if (adev->asic_type == CHIP_RAVEN) { in amdgpu_set_power_dpm_force_performance_level()
2049 enum amd_asic_type asic_type = adev->asic_type; in default_attr_update() local
2059 if (asic_type < CHIP_VEGA10) in default_attr_update()
2062 if (asic_type < CHIP_VEGA10 || asic_type == CHIP_ARCTURUS) in default_attr_update()
2065 if (asic_type < CHIP_VEGA20) in default_attr_update()
2068 if (asic_type == CHIP_ARCTURUS) in default_attr_update()
2076 if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10) in default_attr_update()
2083 if (asic_type != CHIP_VEGA10 && in default_attr_update()
2084 asic_type != CHIP_VEGA20 && in default_attr_update()
2085 asic_type != CHIP_ARCTURUS) in default_attr_update()
[all …]

12345