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Searched refs:bRFMOD (Results 1 – 10 of 10) sorted by relevance

/drivers/staging/rtl8723bs/hal/
Drtl8723b_phycfg.c788 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); in phy_PostSetBwMode8723B()
790 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0); in phy_PostSetBwMode8723B()
799 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); in phy_PostSetBwMode8723B()
801 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1); in phy_PostSetBwMode8723B()
/drivers/staging/rtl8192u/
Dr819xU_phyreg.h107 #define bRFMOD 0x1 macro
Dr819xU_phy.c1475 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); in rtl8192_SetBWModeWorkItem()
1476 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); in rtl8192_SetBWModeWorkItem()
1505 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); in rtl8192_SetBWModeWorkItem()
1506 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); in rtl8192_SetBWModeWorkItem()
/drivers/staging/rtl8712/
Drtl871x_mp.c349 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x0); in r8712_SwitchBandwidth()
350 set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x0); in r8712_SwitchBandwidth()
359 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x1); in r8712_SwitchBandwidth()
360 set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x1); in r8712_SwitchBandwidth()
Drtl871x_mp_phy_regdef.h434 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ macro
/drivers/staging/rtl8188eu/include/
Dhal8188e_phy_reg.h176 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ macro
/drivers/staging/rtl8188eu/hal/
Dphy.c228 phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x0); in phy_set_bw_mode_callback()
229 phy_set_bb_reg(adapt, rFPGA1_RFMOD, bRFMOD, 0x0); in phy_set_bw_mode_callback()
232 phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x1); in phy_set_bw_mode_callback()
233 phy_set_bb_reg(adapt, rFPGA1_RFMOD, bRFMOD, 0x1); in phy_set_bw_mode_callback()
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phy.c1192 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); in _rtl92e_set_bw_mode_work_item()
1193 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); in _rtl92e_set_bw_mode_work_item()
1207 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); in _rtl92e_set_bw_mode_work_item()
1208 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); in _rtl92e_set_bw_mode_work_item()
Dr8192E_phyreg.h273 #define bRFMOD 0x1 macro
/drivers/staging/rtl8723bs/include/
DHal8192CPhyReg.h519 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ macro