| /drivers/gpu/drm/radeon/ |
| D | evergreen_cs.c | 177 unsigned bankw; member
269 palign = (8 * surf->bankw * track->npipes) * surf->mtilea; in evergreen_surface_check_2d()
348 switch (surf->bankw) { in evergreen_surface_value_conv_check()
349 case 0: surf->bankw = 1; break; in evergreen_surface_value_conv_check()
350 case 1: surf->bankw = 2; break; in evergreen_surface_value_conv_check()
351 case 2: surf->bankw = 4; break; in evergreen_surface_value_conv_check()
352 case 3: surf->bankw = 8; break; in evergreen_surface_value_conv_check()
355 __func__, __LINE__, prefix, surf->bankw); in evergreen_surface_value_conv_check()
411 surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
487 surf.bankw, surf.bankh, in evergreen_cs_track_validate_cb()
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| D | radeon_object.c | 682 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; in radeon_bo_set_tiling_flags() local
684 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags()
689 switch (bankw) { in radeon_bo_set_tiling_flags()
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| D | evergreen.c | 1114 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, in evergreen_tiling_fields() argument
1118 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in evergreen_tiling_fields()
1122 switch (*bankw) { in evergreen_tiling_fields()
1124 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break; in evergreen_tiling_fields()
1125 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break; in evergreen_tiling_fields()
1126 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break; in evergreen_tiling_fields()
1127 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break; in evergreen_tiling_fields()
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| D | atombios_crtc.c | 1155 unsigned bankw, bankh, mtaspect, tile_split; in dce4_crtc_do_set_base() local
1276 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1342 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); in dce4_crtc_do_set_base()
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| D | radeon.h | 356 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | dce_v8_0.c | 1910 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v8_0_crtc_do_set_base() local
1912 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base()
1921 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT); in dce_v8_0_crtc_do_set_base()
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| D | dce_v6_0.c | 1938 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v6_0_crtc_do_set_base() local
1940 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v6_0_crtc_do_set_base()
1949 fb_format |= GRPH_BANK_WIDTH(bankw); in dce_v6_0_crtc_do_set_base()
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| D | dce_v10_0.c | 1989 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v10_0_crtc_do_set_base() local
1991 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
2002 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); in dce_v10_0_crtc_do_set_base()
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| D | dce_v11_0.c | 2031 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v11_0_crtc_do_set_base() local
2033 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()
2044 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); in dce_v11_0_crtc_do_set_base()
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm.c | 3979 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; in fill_plane_buffer_attributes() local
3981 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in fill_plane_buffer_attributes()
3992 tiling_info->gfx8.bank_width = bankw; in fill_plane_buffer_attributes()
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