| /drivers/net/ethernet/mellanox/mlx5/core/ |
| D | alloc.c | 183 u32 db_per_page = PAGE_SIZE / cache_line_size(); in mlx5_alloc_db_pgdir()
212 u32 db_per_page = PAGE_SIZE / cache_line_size(); in mlx5_alloc_db_from_pgdir()
224 offset = db->index * cache_line_size(); in mlx5_alloc_db_from_pgdir()
271 u32 db_per_page = PAGE_SIZE / cache_line_size(); in mlx5_db_free()
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| D | main.c | 550 cache_line_size() >= 128 ? 1 : 0); in handle_hca_cap()
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| /drivers/s390/cio/ |
| D | airq.c | 141 if ((cache_line_size() * BITS_PER_BYTE) < bits in airq_iv_create()
306 cache_line_size(), in airq_init()
307 cache_line_size(), PAGE_SIZE); in airq_init()
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| /drivers/infiniband/sw/rxe/ |
| D | rxe_queue.c | 77 if (elem_size < cache_line_size()) in rxe_queue_init()
78 elem_size = cache_line_size(); in rxe_queue_init()
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| /drivers/pci/endpoint/ |
| D | pci-ep-cfs.c | 313 PCI_EPF_HEADER_R(cache_line_size)
314 PCI_EPF_HEADER_W_u8(cache_line_size)
331 CONFIGFS_ATTR(pci_epf_, cache_line_size);
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| /drivers/scsi/cxlflash/ |
| D | common.h | 173 } __aligned(cache_line_size());
228 } __aligned(cache_line_size());
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| D | sislite.h | 480 char carea[cache_line_size()]; /* 128B each */
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| /drivers/staging/vc04_services/interface/vchiq_arm/ |
| D | vchiq_arm.h | 54 const unsigned int cache_line_size; member
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| D | vchiq_2835_arm.c | 100 g_cache_line_size = drvdata->cache_line_size; in vchiq_platform_init()
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| D | vchiq_arm.c | 114 .cache_line_size = 32,
118 .cache_line_size = 64,
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| /drivers/pci/ |
| D | pci-acpi.c | 123 u8 cache_line_size; /* Not applicable to PCIe */ member
131 .cache_line_size = 8,
150 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpx->cache_line_size); in program_hpx_type0()
185 hpx0->cache_line_size = fields[2].integer.value; in decode_type0_hpx_record()
729 hpx0.cache_line_size = fields[0].integer.value; in acpi_run_hpp()
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| D | pci-bridge-emul.h | 14 u8 cache_line_size; member
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| D | pci-bridge-emul.c | 289 bridge->conf.cache_line_size = 0x10; in pci_bridge_emul_init()
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| /drivers/gpu/drm/amd/amdkfd/ |
| D | kfd_crat.h | 166 uint16_t cache_line_size; member
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| D | kfd_crat.c | 321 props->cacheline_size = cache->cache_line_size; in kfd_parse_subtype_cache()
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| /drivers/edac/ |
| D | i7core_edac.c | 1983 const int cache_line_size = 64; in set_sdram_scrub_rate() local
1991 cache_line_size * 1000000; in set_sdram_scrub_rate()
2023 const u32 cache_line_size = 64; in get_sdram_scrub_rate() local
2043 1000000 * cache_line_size; in get_sdram_scrub_rate()
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| D | thunderx_edac.c | 340 unsigned int cline_size = cache_line_size(); in inject_ecc_fn()
411 unsigned int cline_size = cache_line_size(); in thunderx_lmc_inject_ecc_write()
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| /drivers/pci/controller/ |
| D | pcie-rockchip-ep.c | 151 rockchip_pcie_write(rockchip, hdr->cache_line_size, in rockchip_pcie_ep_write_header()
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| /drivers/pci/controller/cadence/ |
| D | pcie-cadence-ep.c | 31 hdr->cache_line_size); in cdns_pcie_ep_write_header()
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| /drivers/pci/controller/dwc/ |
| D | pcie-designware-ep.c | 146 hdr->cache_line_size); in dw_pcie_ep_write_header()
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| /drivers/net/ethernet/marvell/mvpp2/ |
| D | mvpp2.h | 755 ETH_HLEN + ETH_FCS_LEN, cache_line_size())
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| /drivers/net/ethernet/mellanox/mlx4/ |
| D | fw.c | 1904 ((ilog2(cache_line_size()) - 4) << 5) | (1 << 4); in mlx4_INIT_HCA()
1953 dev->caps.eqe_size = cache_line_size(); in mlx4_INIT_HCA()
1954 dev->caps.cqe_size = cache_line_size(); in mlx4_INIT_HCA()
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| D | main.c | 381 if (cache_line_size() == 128 || cache_line_size() == 256) { in mlx4_enable_cqe_eqe_stride()
390 if (cache_line_size() != 32 && cache_line_size() != 64) in mlx4_enable_cqe_eqe_stride()
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| /drivers/net/ethernet/qlogic/qed/ |
| D | qed_dev.c | 2529 u32 val, wr_mbs, cache_line_size; in qed_init_cache_line_size() local
2549 cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs); in qed_init_cache_line_size()
2550 switch (cache_line_size) { in qed_init_cache_line_size()
2566 cache_line_size); in qed_init_cache_line_size()
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| /drivers/iommu/ |
| D | iova.c | 973 rcache->cpu_rcaches = __alloc_percpu(sizeof(*cpu_rcache), cache_line_size()); in init_iova_rcaches()
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