| /drivers/staging/mt7621-dts/ |
| D | mt7621.dtsi | 5 #address-cells = <1>;
6 #size-cells = <1>;
20 #address-cells = <0>;
21 #interrupt-cells = <1>;
31 #clock-cells = <0>;
39 #clock-cells = <0>;
47 #clock-cells = <0>;
75 #address-cells = <1>;
76 #size-cells = <1>;
89 #gpio-cells = <2>;
[all …]
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| /drivers/mfd/ |
| D | sky81452.c | 29 struct mfd_cell cells[2]; in sky81452_probe() local
47 memset(cells, 0, sizeof(cells)); in sky81452_probe()
48 cells[0].name = "sky81452-backlight"; in sky81452_probe()
49 cells[0].of_compatible = "skyworks,sky81452-backlight"; in sky81452_probe()
50 cells[1].name = "sky81452-regulator"; in sky81452_probe()
51 cells[1].platform_data = pdata->regulator_init_data; in sky81452_probe()
52 cells[1].pdata_size = sizeof(*pdata->regulator_init_data); in sky81452_probe()
54 ret = devm_mfd_add_devices(dev, -1, cells, ARRAY_SIZE(cells), in sky81452_probe()
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| D | lpc_sch.c | 137 unsigned int cells = 0; in lpc_sch_probe() local
142 id->device, &lpc_sch_cells[cells]); in lpc_sch_probe()
146 cells++; in lpc_sch_probe()
150 id->device, &lpc_sch_cells[cells]); in lpc_sch_probe()
154 cells++; in lpc_sch_probe()
158 id->device, &lpc_sch_cells[cells]); in lpc_sch_probe()
162 cells++; in lpc_sch_probe()
164 if (cells == 0) { in lpc_sch_probe()
169 return mfd_add_devices(&dev->dev, 0, lpc_sch_cells, cells, NULL, 0, NULL); in lpc_sch_probe()
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| D | wm97xx-core.c | 256 struct mfd_cell *cells; in wm97xx_ac97_probe() local
282 cells = wm9705_cells; in wm97xx_ac97_probe()
287 cells = wm9712_cells; in wm97xx_ac97_probe()
292 cells = wm9713_cells; in wm97xx_ac97_probe()
300 cells[i].platform_data = codec_pdata; in wm97xx_ac97_probe()
301 cells[i].pdata_size = sizeof(*codec_pdata); in wm97xx_ac97_probe()
311 cells, nb_cells, NULL, 0, NULL); in wm97xx_ac97_probe()
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| /drivers/of/unittest-data/ |
| D | tests-address.dtsi | 4 #address-cells = <1>;
5 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <1>;
26 #address-cells = <2>;
27 #size-cells = <2>;
38 #address-cells = <3>;
39 #size-cells = <2>;
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| D | tests-interrupts.dtsi | 6 #address-cells = <1>;
7 #size-cells = <1>;
10 #interrupt-cells = <1>;
15 #interrupt-cells = <3>;
20 #interrupt-cells = <2>;
24 #interrupt-cells = <1>;
25 #address-cells = <0>;
33 #interrupt-cells = <2>;
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| D | tests-overlay.dtsi | 10 #address-cells = <1>;
11 #size-cells = <0>;
78 #address-cells = <1>;
79 #size-cells = <0>;
98 #address-cells = <1>;
99 #size-cells = <0>;
102 #address-cells = <1>;
103 #size-cells = <0>;
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| D | overlay_15.dts | 8 #address-cells = <1>;
9 #size-cells = <0>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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| D | tests-platform.dtsi | 6 #address-cells = <1>;
7 #size-cells = <0>;
13 #address-cells = <1>;
14 #size-cells = <0>;
26 #address-cells = <1>;
27 #size-cells = <0>;
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| D | overlay.dts | 18 #address-cells = <1>;
19 #size-cells = <1>;
23 #address-cells = <1>;
24 #size-cells = <1>;
36 #address-cells = <1>;
37 #size-cells = <1>;
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| D | tests-phandle.dtsi | 14 #phandle-cells = <0>;
18 #phandle-cells = <1>;
22 #phandle-cells = <2>;
26 #phandle-cells = <3>;
30 #phandle-cells = <2>;
42 #phandle-cells = <2>;
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| D | overlay_base.dts | 16 #address-cells = <1>;
17 #size-cells = <1>;
42 #address-cells = <1>;
43 #size-cells = <1>;
49 #address-cells = <1>;
50 #size-cells = <1>;
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| D | overlay_10.dts | 10 #address-cells = <1>;
11 #size-cells = <0>;
18 #address-cells = <1>;
19 #size-cells = <0>;
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| D | overlay_11.dts | 10 #address-cells = <1>;
11 #size-cells = <0>;
18 #address-cells = <1>;
19 #size-cells = <0>;
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| /drivers/staging/mt7621-pci/ |
| D | mediatek,mt7621-pci.txt | 8 - #address-cells: Address representation for root ports (must be 3)
11 - #size-cells: Size representation for root ports (must be 2)
13 - #interrupt-cells: Must be 1
34 - #address-cells: Must be 3
35 - #size-cells: Must be 2
49 #address-cells = <3>;
50 #size-cells = <2>;
63 #interrupt-cells = <1>;
82 #address-cells = <3>;
83 #size-cells = <2>;
[all …]
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| /drivers/clk/mmp/ |
| D | clk-of-pxa910.c | 237 struct mmp_clk_reset_cell *cells; in pxa910_clk_reset_init() local
243 cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL); in pxa910_clk_reset_init()
244 if (!cells) in pxa910_clk_reset_init()
249 cells[base + i].clk_id = apbc_gate_clks[i].id; in pxa910_clk_reset_init()
250 cells[base + i].reg = in pxa910_clk_reset_init()
252 cells[base + i].flags = 0; in pxa910_clk_reset_init()
253 cells[base + i].lock = apbc_gate_clks[i].lock; in pxa910_clk_reset_init()
254 cells[base + i].bits = 0x4; in pxa910_clk_reset_init()
259 cells[base + i].clk_id = apbcp_gate_clks[i].id; in pxa910_clk_reset_init()
260 cells[base + i].reg = in pxa910_clk_reset_init()
[all …]
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| D | clk-of-pxa1928.c | 186 struct mmp_clk_reset_cell *cells; in pxa1928_clk_reset_init() local
190 cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL); in pxa1928_clk_reset_init()
191 if (!cells) in pxa1928_clk_reset_init()
196 cells[base + i].clk_id = apbc_gate_clks[i].id; in pxa1928_clk_reset_init()
197 cells[base + i].reg = in pxa1928_clk_reset_init()
199 cells[base + i].flags = 0; in pxa1928_clk_reset_init()
200 cells[base + i].lock = apbc_gate_clks[i].lock; in pxa1928_clk_reset_init()
201 cells[base + i].bits = 0x4; in pxa1928_clk_reset_init()
204 mmp_clk_reset_register(np, cells, nr_resets); in pxa1928_clk_reset_init()
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| D | reset.c | 23 cell = &unit->cells[i]; in mmp_of_reset_xlate()
42 cell = &unit->cells[id]; in mmp_clk_reset_assert()
64 cell = &unit->cells[id]; in mmp_clk_reset_deassert()
84 struct mmp_clk_reset_cell *cells, int nr_resets) in mmp_clk_reset_register() argument
92 unit->cells = cells; in mmp_clk_reset_register()
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| D | clk-of-pxa168.c | 231 struct mmp_clk_reset_cell *cells; in pxa168_clk_reset_init() local
235 cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL); in pxa168_clk_reset_init()
236 if (!cells) in pxa168_clk_reset_init()
240 cells[i].clk_id = apbc_gate_clks[i].id; in pxa168_clk_reset_init()
241 cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset; in pxa168_clk_reset_init()
242 cells[i].flags = 0; in pxa168_clk_reset_init()
243 cells[i].lock = apbc_gate_clks[i].lock; in pxa168_clk_reset_init()
244 cells[i].bits = 0x4; in pxa168_clk_reset_init()
247 mmp_clk_reset_register(np, cells, nr_resets); in pxa168_clk_reset_init()
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| /drivers/gpu/drm/rcar-du/ |
| D | rcar_du_of_lvds_r8a7790.dts | 12 #address-cells = <2>;
13 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
41 #address-cells = <1>;
42 #size-cells = <0>;
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| D | rcar_du_of_lvds_r8a7791.dts | 12 #address-cells = <2>;
13 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
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| D | rcar_du_of_lvds_r8a7793.dts | 12 #address-cells = <2>;
13 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
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| D | rcar_du_of_lvds_r8a7795.dts | 12 #address-cells = <2>;
13 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
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| D | rcar_du_of_lvds_r8a7796.dts | 12 #address-cells = <2>;
13 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
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| /drivers/iommu/ |
| D | of_iommu.c | 59 u32 cells; in of_get_dma_window() local
70 cells = prop ? be32_to_cpup(prop) : of_n_addr_cells(dn); in of_get_dma_window()
71 if (!cells) in of_get_dma_window()
73 *addr = of_read_number(dma_window, cells); in of_get_dma_window()
74 dma_window += cells; in of_get_dma_window()
77 cells = prop ? be32_to_cpup(prop) : of_n_size_cells(dn); in of_get_dma_window()
78 if (!cells) in of_get_dma_window()
80 *size = of_read_number(dma_window, cells); in of_get_dma_window()
81 dma_window += cells; in of_get_dma_window()
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