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Searched refs:cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_6_1_offset.h703 #define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT … macro
Dnbio_7_4_offset.h962 #define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT … macro
Dnbio_2_3_offset.h2074 #define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT … macro