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Searched refs:cgs_read_ind_register (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu_helper.h142 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
146 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
155 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
160 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
Dvega10_powertune.c785 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset); in vega10_program_didt_config_registers()
791 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset); in vega10_program_didt_config_registers()
797 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset); in vega10_program_didt_config_registers()
868 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL); in vega10_didt_set_mask()
875 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL); in vega10_didt_set_mask()
882 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL); in vega10_didt_set_mask()
889 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL); in vega10_didt_set_mask()
896 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL); in vega10_didt_set_mask()
Dsmu8_hwmgr.c1554 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, in smu8_print_clock_levels()
1566 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, in smu8_print_clock_levels()
1689 uint32_t val = cgs_read_ind_register(hwmgr->device, in smu8_thermal_get_temperature()
1715 …uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGE… in smu8_read_sensor()
1717 …uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET… in smu8_read_sensor()
1719 …uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET… in smu8_read_sensor()
1740 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) & in smu8_read_sensor()
1746 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) & in smu8_read_sensor()
Dsmu7_hwmgr.c156 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE, in smu7_get_current_pcie_speed()
392 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, in smu7_enable_display_gap()
519 tmp = (cgs_read_ind_register(hwmgr->device, in smu7_force_switch_to_arbf0()
1110 soft_register_value = cgs_read_ind_register(hwmgr->device, in smu7_disable_sclk_vce_handshake()
1126 soft_register_value = cgs_read_ind_register(hwmgr->device, in smu7_disable_handshake_uvd()
2246 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL); in smu7_thermal_parameter_init()
3611 tmp = cgs_read_ind_register(hwmgr->device, in smu7_get_gpu_power()
3652 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset); in smu7_read_sensor()
4177 …uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNT… in smu7_program_display_gap()
4388 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL); in smu7_read_clock_registers()
[all …]
Dsmu7_powertune.c913 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset); in smu7_program_pt_config_registers()
917 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset); in smu7_program_pt_config_registers()
921 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset); in smu7_program_pt_config_registers()
/drivers/gpu/drm/amd/include/
Dcgs_common.h134 …cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~C…
169 #define cgs_read_ind_register(dev,space,index) \ macro
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dfiji_smumgr.c1680 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_populate_clock_stretcher_data_table()
1682 efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_populate_clock_stretcher_data_table()
1739 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_populate_clock_stretcher_data_table()
1812 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL); in fiji_populate_clock_stretcher_data_table()
2382 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, in fiji_update_uvd_smc_table()
2418 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, in fiji_update_vce_smc_table()
2585 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in fiji_update_dpm_settings()
2599 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in fiji_update_dpm_settings()
2620 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in fiji_update_dpm_settings()
2634 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in fiji_update_dpm_settings()
Dtonga_smumgr.c1597 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, in tonga_populate_clock_stretcher_data_table()
1599 efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, in tonga_populate_clock_stretcher_data_table()
1666 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, in tonga_populate_clock_stretcher_data_table()
1737 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, in tonga_populate_clock_stretcher_data_table()
2691 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, in tonga_update_uvd_smc_table()
2726 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, in tonga_update_vce_smc_table()
3182 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in tonga_update_dpm_settings()
3196 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in tonga_update_dpm_settings()
3217 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in tonga_update_dpm_settings()
3231 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in tonga_update_dpm_settings()
Dpolaris10_smumgr.c327 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4)); in polaris10_is_hw_avfs_present()
1528 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, in polaris10_populate_clock_stretcher_data_table()
1589 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL); in polaris10_populate_clock_stretcher_data_table()
2196 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, in polaris10_update_uvd_smc_table()
2232 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, in polaris10_update_vce_smc_table()
2503 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in polaris10_update_dpm_settings()
2517 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in polaris10_update_dpm_settings()
2538 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in polaris10_update_dpm_settings()
2552 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in polaris10_update_dpm_settings()
Dvegam_smumgr.c346 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, in vegam_update_uvd_smc_table()
382 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, in vegam_update_vce_smc_table()
1542 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL); in vegam_populate_clock_stretcher_data_table()
1553 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, in vegam_is_hw_avfs_present()
Dci_smumgr.c191 && (0x20100 <= cgs_read_ind_register(hwmgr->device, in ci_is_smc_ram_running()
2793 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in ci_update_dpm_settings()
2807 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in ci_update_dpm_settings()
2828 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in ci_update_dpm_settings()
2842 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); in ci_update_dpm_settings()
Dsmu7_smumgr.c163 && (0x20100 <= cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMC_PC_C))); in smu7_is_smc_ram_running()
Diceland_smumgr.c211 val = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, in iceland_smu_upload_firmware_image()
/drivers/gpu/drm/amd/display/dc/
Ddm_services.h94 return cgs_read_ind_register(ctx->cgs_device, addr_space, index); in dm_read_index_reg()