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Searched refs:clk_mgr (Results 1 – 25 of 49) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr.c55 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
58 (clk_mgr->regs->reg)
86 static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *ent… in dcn3_init_single_clock() argument
90 uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF); in dcn3_init_single_clock()
102 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF); in dcn3_init_single_clock()
103 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn3_init_single_clock()
107 static void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr) in dcn3_build_wm_range_table() argument
110 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn3_build_wm_range_table()
111 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; in dcn3_build_wm_range_table()
112 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn3_build_wm_range_table()
[all …]
Ddcn30_clk_mgr_smu_msg.c52 static uint32_t dcn30_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us… in dcn30_smu_wait_for_response() argument
74 static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32… in dcn30_smu_send_msg_with_param() argument
77 dcn30_smu_wait_for_response(clk_mgr, 10, 200000); in dcn30_smu_send_msg_with_param()
89 if (dcn30_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) { in dcn30_smu_send_msg_with_param()
100 bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input) in dcn30_smu_test_message() argument
106 if (dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_test_message()
114 bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version) in dcn30_smu_get_smu_version() argument
118 if (dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_get_smu_version()
130 bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr) in dcn30_smu_check_driver_if_version() argument
136 if (dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_check_driver_if_version()
[all …]
Ddcn30_clk_mgr_smu_msg.h91 bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input);
92 bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version);
93 bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);
94 bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);
95 void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
96 void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
97 void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
98 void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
99 unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t…
100 unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t…
[all …]
Ddcn30_clk_mgr.h29 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base);
32 struct clk_mgr_internal *clk_mgr,
36 void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c43 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
46 (clk_mgr->regs->reg)
103 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, in dcn20_update_clocks_update_dpp_dto() argument
108 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
109 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
118 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; in dcn20_update_clocks_update_dpp_dto()
121 clk_mgr->dccg->funcs->update_dpp_dto( in dcn20_update_clocks_update_dpp_dto()
122 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn20_update_clocks_update_dpp_dto()
126 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr) in dcn20_update_clocks_update_dentist() argument
129 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dentist()
[all …]
Ddcn20_clk_mgr.h29 void dcn2_update_clocks(struct clk_mgr *dccg,
33 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
36 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
39 void dcn2_init_clocks(struct clk_mgr *clk_mgr);
42 struct clk_mgr_internal *clk_mgr,
48 void dcn2_get_clock(struct clk_mgr *clk_mgr,
53 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr);
55 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr.c37 void rv1_init_clocks(struct clk_mgr *clk_mgr) in rv1_init_clocks() argument
39 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in rv1_init_clocks()
42 static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_c… in rv1_determine_dppclk_threshold() argument
45 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz; in rv1_determine_dppclk_threshold()
47 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz; in rv1_determine_dppclk_threshold()
77 if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold) in rv1_determine_dppclk_threshold()
89 struct clk_mgr_internal *clk_mgr, in ramp_up_dispclk_with_dpp() argument
95 int dispclk_to_dpp_threshold = rv1_determine_dppclk_threshold(clk_mgr, new_clocks); in ramp_up_dispclk_with_dpp()
161 clk_mgr->funcs->set_dispclk(clk_mgr, dispclk_to_dpp_threshold); in ramp_up_dispclk_with_dpp()
162 clk_mgr->funcs->set_dprefclk(clk_mgr); in ramp_up_dispclk_with_dpp()
[all …]
Drv1_clk_mgr_vbios_smu.c84 static uint32_t rv1_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, … in rv1_smu_wait_for_response() argument
102 int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsign… in rv1_vbios_smu_send_msg_with_param() argument
115 result = rv1_smu_wait_for_response(clk_mgr, 10, 1000); in rv1_vbios_smu_send_msg_with_param()
123 int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in rv1_vbios_smu_set_dispclk() argument
126 struct dc *dc = clk_mgr->base.ctx->dc; in rv1_vbios_smu_set_dispclk()
131 clk_mgr, in rv1_vbios_smu_set_dispclk()
137 if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz) in rv1_vbios_smu_set_dispclk()
146 int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in rv1_vbios_smu_set_dprefclk() argument
151 clk_mgr, in rv1_vbios_smu_set_dprefclk()
153 clk_mgr->base.dprefclk_khz / 1000); in rv1_vbios_smu_set_dprefclk()
Drv2_clk_mgr.c37 void rv2_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_… in rv2_clk_mgr_construct() argument
40 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); in rv2_clk_mgr_construct()
42 clk_mgr->funcs = &rv2_clk_internal_funcs; in rv2_clk_mgr_construct()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr_vbios_smu.c70 static uint32_t rn_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, u… in rn_smu_wait_for_response() argument
89 int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigne… in rn_vbios_smu_send_msg_with_param() argument
102 result = rn_smu_wait_for_response(clk_mgr, 10, 1000); in rn_vbios_smu_send_msg_with_param()
110 int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in rn_vbios_smu_get_smu_version() argument
113 clk_mgr, in rn_vbios_smu_get_smu_version()
119 int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in rn_vbios_smu_set_dispclk() argument
122 struct dc *dc = clk_mgr->base.ctx->dc; in rn_vbios_smu_set_dispclk()
127 clk_mgr, in rn_vbios_smu_set_dispclk()
133 if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz) in rn_vbios_smu_set_dispclk()
142 int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in rn_vbios_smu_set_dprefclk() argument
[all …]
Drn_clk_mgr.c99 void rn_set_low_power_state(struct clk_mgr *clk_mgr_base) in rn_set_low_power_state()
101 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rn_set_low_power_state() local
103 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER); in rn_set_low_power_state()
108 void rn_update_clocks(struct clk_mgr *clk_mgr_base, in rn_update_clocks()
112 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rn_update_clocks() local
136 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER); in rn_update_clocks()
144 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE); in rn_update_clocks()
152 rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); in rn_update_clocks()
158 rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); in rn_update_clocks()
186 rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); in rn_update_clocks()
[all …]
Drn_clk_mgr_vbios_smu.h29 int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
30 int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
31 int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
32 int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
33 int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_d…
34 void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
35 int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
36 void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, int display_count);
37 void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
38 void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
[all …]
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dclk_mgr.h227 void (*update_clocks)(struct clk_mgr *clk_mgr,
231 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr);
233 void (*set_low_power_state)(struct clk_mgr *clk_mgr);
235 void (*init_clocks)(struct clk_mgr *clk_mgr);
237 void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
238 void (*get_clock)(struct clk_mgr *clk_mgr,
245 void (*notify_wm_ranges)(struct clk_mgr *clk_mgr);
248 void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link);
255 void (*set_hard_min_memclk)(struct clk_mgr *clk_mgr, bool current_mode);
258 void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr);
[all …]
Dclk_mgr_internal.h69 #define TO_CLK_MGR_INTERNAL(clk_mgr)\ argument
70 container_of(clk_mgr, struct clk_mgr_internal, base)
73 clk_mgr->base.ctx
76 clk_mgr->base.ctx->logger
218 struct clk_mgr base;
297 int (*set_dispclk)(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
298 int (*set_dprefclk)(struct clk_mgr_internal *clk_mgr);
/drivers/gpu/drm/amd/display/dc/clk_mgr/
Dclk_mgr.c89 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr) in clk_mgr_exit_optimized_pwr_state() argument
97 clk_mgr->psr_allow_active_cache = edp_link->psr_settings.psr_allow_active; in clk_mgr_exit_optimized_pwr_state()
103 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr) in clk_mgr_optimize_pwr_state() argument
108 dc_link_set_psr_allow_active(edp_link, clk_mgr->psr_allow_active_cache, false); in clk_mgr_optimize_pwr_state()
115 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg … in dc_clk_mgr_create()
119 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local
121 if (clk_mgr == NULL) { in dc_clk_mgr_create()
129 dce60_clk_mgr_construct(ctx, clk_mgr); in dc_clk_mgr_create()
134 dce_clk_mgr_construct(ctx, clk_mgr); in dc_clk_mgr_create()
137 dce110_clk_mgr_construct(ctx, clk_mgr); in dc_clk_mgr_create()
[all …]
DMakefile26 CLK_MGR = clk_mgr.o
28 AMD_DAL_CLK_MGR = $(addprefix $(AMDDALPATH)/dc/clk_mgr/,$(CLK_MGR))
39 AMD_DAL_CLK_MGR_DCE60 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce60/,$(CLK_MGR_DCE60))
49 AMD_DAL_CLK_MGR_DCE100 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce100/,$(CLK_MGR_DCE100))
58 AMD_DAL_CLK_MGR_DCE110 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce110/,$(CLK_MGR_DCE110))
66 AMD_DAL_CLK_MGR_DCE112 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce112/,$(CLK_MGR_DCE112))
74 AMD_DAL_CLK_MGR_DCE120 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce120/,$(CLK_MGR_DCE120))
83 AMD_DAL_CLK_MGR_DCN10 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn10/,$(CLK_MGR_DCN10))
92 AMD_DAL_CLK_MGR_DCN20 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn20/,$(CLK_MGR_DCN20))
104 CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn21/rn_clk_mgr.o := $(call cc-option,-mno-gnu-attribute)
[all …]
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clk_mgr.c48 clk_mgr->ctx->logger
148 static int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr) in dce_get_dp_ref_freq_khz() argument
150 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); in dce_get_dp_ref_freq_khz()
174 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr) in dce12_get_dp_ref_freq_khz() argument
176 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); in dce12_get_dp_ref_freq_khz()
214 struct clk_mgr *clk_mgr, in dce_get_required_clocks_state() argument
217 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); in dce_get_required_clocks_state()
247 struct clk_mgr *clk_mgr, in dce_set_clock() argument
250 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); in dce_set_clock()
252 struct dc_bios *bp = clk_mgr->ctx->dc_bios; in dce_set_clock()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/
Ddce60_clk_mgr.c47 (clk_mgr->regs->reg)
51 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
83 static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce60_get_dp_ref_freq_khz()
85 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce60_get_dp_ref_freq_khz() local
101 * clk_mgr->base.dentist_vco_freq_khz) / target_div; in dce60_get_dp_ref_freq_khz()
103 return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz); in dce60_get_dp_ref_freq_khz()
120 static void dce60_update_clocks(struct clk_mgr *clk_mgr_base, in dce60_update_clocks()
161 struct clk_mgr_internal *clk_mgr) in dce60_clk_mgr_construct() argument
163 dce_clk_mgr_construct(ctx, clk_mgr); in dce60_clk_mgr_construct()
165 memcpy(clk_mgr->max_clks_by_state, in dce60_clk_mgr_construct()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
Ddce_clk_mgr.c47 (clk_mgr->regs->reg)
51 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
129 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce_get_dp_ref_freq_khz()
131 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce_get_dp_ref_freq_khz() local
150 * clk_mgr->base.dentist_vco_freq_khz) / target_div; in dce_get_dp_ref_freq_khz()
152 return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz); in dce_get_dp_ref_freq_khz()
155 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce12_get_dp_ref_freq_khz()
195 struct clk_mgr *clk_mgr_base, in dce_get_required_clocks_state()
230 struct clk_mgr *clk_mgr_base, in dce_set_clock()
395 static void dce_update_clocks(struct clk_mgr *clk_mgr_base, in dce_update_clocks()
[all …]
Ddce_clk_mgr.h34 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base);
36 struct clk_mgr *clk_mgr_base,
48 int dce12_get_dp_ref_freq_khz(struct clk_mgr *dccg);
51 struct clk_mgr *clk_mgr_base,
55 void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
Ddce112_clk_mgr.c70 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz) in dce112_set_clock()
124 int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz) in dce112_set_dispclk() argument
127 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; in dce112_set_dispclk()
128 struct dc *dc = clk_mgr->base.ctx->dc; in dce112_set_dispclk()
137 clk_mgr->base.dentist_vco_freq_khz / 62); in dce112_set_dispclk()
151 clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; in dce112_set_dispclk()
156 if (clk_mgr->dfs_bypass_disp_clk != actual_clock) in dce112_set_dispclk()
162 clk_mgr->dfs_bypass_disp_clk = actual_clock; in dce112_set_dispclk()
167 int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dce112_set_dprefclk() argument
170 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; in dce112_set_dprefclk()
[all …]
Ddce112_clk_mgr.h32 struct clk_mgr_internal *clk_mgr);
35 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz);
36 int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz);
37 int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
Ddce120_clk_mgr.c84 static void dce12_update_clocks(struct clk_mgr *clk_mgr_base, in dce12_update_clocks()
128 void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr) in dce120_clk_mgr_construct() argument
130 dce_clk_mgr_construct(ctx, clk_mgr); in dce120_clk_mgr_construct()
132 memcpy(clk_mgr->max_clks_by_state, in dce120_clk_mgr_construct()
136 clk_mgr->base.dprefclk_khz = 600000; in dce120_clk_mgr_construct()
137 clk_mgr->base.funcs = &dce120_funcs; in dce120_clk_mgr_construct()
140 void dce121_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr) in dce121_clk_mgr_construct() argument
142 dce120_clk_mgr_construct(ctx, clk_mgr); in dce121_clk_mgr_construct()
143 clk_mgr->base.dprefclk_khz = 625000; in dce121_clk_mgr_construct()
150 dce121_clock_patch_xgmi_ss_info(clk_mgr); in dce121_clk_mgr_construct()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
Ddce110_clk_mgr.c230 pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz; in dce11_pplib_apply_display_requirements()
248 static void dce11_update_clocks(struct clk_mgr *clk_mgr_base, in dce11_update_clocks()
282 struct clk_mgr_internal *clk_mgr) in dce110_clk_mgr_construct() argument
284 dce_clk_mgr_construct(ctx, clk_mgr); in dce110_clk_mgr_construct()
286 memcpy(clk_mgr->max_clks_by_state, in dce110_clk_mgr_construct()
290 clk_mgr->regs = &disp_clk_regs; in dce110_clk_mgr_construct()
291 clk_mgr->clk_mgr_shift = &disp_clk_shift; in dce110_clk_mgr_construct()
292 clk_mgr->clk_mgr_mask = &disp_clk_mask; in dce110_clk_mgr_construct()
293 clk_mgr->base.funcs = &dce110_funcs; in dce110_clk_mgr_construct()
/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_hw_sequencer.c114 dc->clk_mgr->funcs->update_clocks( in dce100_prepare_bandwidth()
115 dc->clk_mgr, in dce100_prepare_bandwidth()
126 dc->clk_mgr->funcs->update_clocks( in dce100_optimize_bandwidth()
127 dc->clk_mgr, in dce100_optimize_bandwidth()

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