| /drivers/clk/samsung/ |
| D | clk-s5pv210-audss.c | 70 struct clk_hw **clk_table; in s5pv210_audss_clk_probe() local
88 clk_table = clk_data->hws; in s5pv210_audss_clk_probe()
117 clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", in s5pv210_audss_clk_probe()
128 clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss", in s5pv210_audss_clk_probe()
133 clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
136 clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
140 clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss", in s5pv210_audss_clk_probe()
146 clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss", in s5pv210_audss_clk_probe()
149 clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss", in s5pv210_audss_clk_probe()
152 clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss", in s5pv210_audss_clk_probe()
[all …]
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| D | clk-s3c2410-dclk.c | 245 struct clk_hw **clk_table; in s3c24xx_dclk_probe() local
255 clk_table = s3c24xx_dclk->clk_data.hws; in s3c24xx_dclk_probe()
270 clk_table[MUX_DCLK0] = clk_hw_register_mux(&pdev->dev, "mux_dclk0", in s3c24xx_dclk_probe()
275 clk_table[MUX_DCLK1] = clk_hw_register_mux(&pdev->dev, "mux_dclk1", in s3c24xx_dclk_probe()
281 clk_table[DIV_DCLK0] = clk_hw_register_divider(&pdev->dev, "div_dclk0", in s3c24xx_dclk_probe()
284 clk_table[DIV_DCLK1] = clk_hw_register_divider(&pdev->dev, "div_dclk1", in s3c24xx_dclk_probe()
288 clk_table[GATE_DCLK0] = clk_hw_register_gate(&pdev->dev, "gate_dclk0", in s3c24xx_dclk_probe()
292 clk_table[GATE_DCLK1] = clk_hw_register_gate(&pdev->dev, "gate_dclk1", in s3c24xx_dclk_probe()
297 clk_table[MUX_CLKOUT0] = s3c24xx_register_clkout(&pdev->dev, in s3c24xx_dclk_probe()
300 clk_table[MUX_CLKOUT1] = s3c24xx_register_clkout(&pdev->dev, in s3c24xx_dclk_probe()
[all …]
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| D | clk-exynos-audss.c | 131 struct clk_hw **clk_table; in exynos_audss_clk_probe() local
155 clk_table = clk_data->hws; in exynos_audss_clk_probe()
186 clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss", in exynos_audss_clk_probe()
197 clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s", in exynos_audss_clk_probe()
202 clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp", in exynos_audss_clk_probe()
206 clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev, in exynos_audss_clk_probe()
210 clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s", in exynos_audss_clk_probe()
214 clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk", in exynos_audss_clk_probe()
218 clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus", in exynos_audss_clk_probe()
222 clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s", in exynos_audss_clk_probe()
[all …]
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| /drivers/clk/mmp/ |
| D | clk.c | 13 struct clk **clk_table; in mmp_clk_init() local
15 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); in mmp_clk_init()
16 if (!clk_table) in mmp_clk_init()
19 unit->clk_table = clk_table; in mmp_clk_init()
21 unit->clk_data.clks = clk_table; in mmp_clk_init()
44 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
66 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_factor_clks()
92 unit->clk_table[clks[i].id] = clk; in mmp_register_general_gate_clks()
120 unit->clk_table[clks[i].id] = clk; in mmp_register_gate_clks()
148 unit->clk_table[clks[i].id] = clk; in mmp_register_mux_clks()
[all …]
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| D | clk-pll.c | 168 unit->clk_table[clks[i].id] = clk; in mmp_register_pll_clks()
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| D | clk.h | 138 struct clk **clk_table; member
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| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | vega10_processpptables.c | 575 phm_ppt_v1_clock_voltage_dependency_table *clk_table; in get_socclk_voltage_dependency_table() local
584 clk_table = kzalloc(table_size, GFP_KERNEL); in get_socclk_voltage_dependency_table()
586 if (!clk_table) in get_socclk_voltage_dependency_table()
589 clk_table->count = (uint32_t)clk_dep_table->ucNumEntries; in get_socclk_voltage_dependency_table()
592 clk_table->entries[i].vddInd = in get_socclk_voltage_dependency_table()
594 clk_table->entries[i].clk = in get_socclk_voltage_dependency_table()
598 *pp_vega10_clk_dep_table = clk_table; in get_socclk_voltage_dependency_table()
649 *clk_table; in get_gfxclk_voltage_dependency_table() local
659 clk_table = kzalloc(table_size, GFP_KERNEL); in get_gfxclk_voltage_dependency_table()
661 if (!clk_table) in get_gfxclk_voltage_dependency_table()
[all …]
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| D | process_pptables_v1_0.c | 317 struct phm_clock_array **clk_table, in get_valid_clk() argument
344 *clk_table = table; in get_valid_clk()
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| /drivers/clk/hisilicon/ |
| D | clk.c | 31 struct clk **clk_table; in hisi_clk_alloc() local
45 clk_table = devm_kmalloc_array(&pdev->dev, nr_clks, in hisi_clk_alloc()
46 sizeof(*clk_table), in hisi_clk_alloc()
48 if (!clk_table) in hisi_clk_alloc()
51 clk_data->clk_data.clks = clk_table; in hisi_clk_alloc()
62 struct clk **clk_table; in hisi_clk_init() local
76 clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL); in hisi_clk_init()
77 if (!clk_table) in hisi_clk_init()
80 clk_data->clk_data.clks = clk_table; in hisi_clk_init()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 103 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn3_init_single_clock()
113 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn3_build_wm_range_table()
175 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks()
180 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn3_init_clocks()
187 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, in dcn3_init_clocks()
192 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, in dcn3_init_clocks()
197 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz, in dcn3_init_clocks()
292 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_update_clocks()
388 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); in dcn3_set_hard_min_memclk()
400 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_set_hard_max_memclk()
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| /drivers/clk/axis/ |
| D | clk-artpec6.c | 20 struct clk *clk_table[ARTPEC6_CLK_NUMCLOCKS]; member
56 clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
107 clkdata->clk_data.clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
121 struct clk **clks = clkdata->clk_table; in artpec6_clkctrl_probe()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 448 …ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcf… in build_watermark_ranges()
450 …ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_… in build_watermark_ranges()
547 .clk_table = {
805 bw_params->clk_table.num_entries = j + 1; in rn_clk_mgr_helper_populate_bw_params()
807 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { in rn_clk_mgr_helper_populate_bw_params()
808 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
809 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
810 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol; in rn_clk_mgr_helper_populate_bw_params()
811 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FCl… in rn_clk_mgr_helper_populate_bw_params()
820 if (i >= bw_params->clk_table.num_entries) { in rn_clk_mgr_helper_populate_bw_params()
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| /drivers/clk/socfpga/ |
| D | clk-agilex.c | 409 struct clk **clk_table; in __socfpga_agilex_clk_init() local
424 clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL); in __socfpga_agilex_clk_init()
425 if (!clk_table) in __socfpga_agilex_clk_init()
428 clk_data->clk_data.clks = clk_table; in __socfpga_agilex_clk_init()
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| D | clk-s10.c | 392 struct clk **clk_table; in __socfpga_s10_clk_init() local
408 clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL); in __socfpga_s10_clk_init()
409 if (!clk_table) in __socfpga_s10_clk_init()
412 clk_data->clk_data.clks = clk_table; in __socfpga_s10_clk_init()
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| /drivers/acpi/pmic/ |
| D | tps68470_pmic.c | 168 static const struct tps68470_pmic_table clk_table[] = { variable
330 clk_table, in tps68470_pmic_clk_handler()
331 ARRAY_SIZE(clk_table)); in tps68470_pmic_clk_handler()
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 1142 vlevel_max = bw_params->clk_table.num_entries - 1; in dcn21_calculate_wm()
1406 struct clk_limit_table *clk_table = &bw_params->clk_table; in update_bw_bounding_box() local
1417 ASSERT(clk_table->num_entries); in update_bw_bounding_box()
1418 for (i = 0; i < clk_table->num_entries; i++) { in update_bw_bounding_box()
1421 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in update_bw_bounding_box()
1428 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in update_bw_bounding_box()
1429 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; in update_bw_bounding_box()
1430 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; in update_bw_bounding_box()
1431 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; in update_bw_bounding_box()
1441 for (i = 0; i < clk_table->num_entries; i++) in update_bw_bounding_box()
[all …]
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| /drivers/clk/rockchip/ |
| D | clk.c | 368 struct clk **clk_table; in rockchip_clk_init() local
375 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); in rockchip_clk_init()
376 if (!clk_table) in rockchip_clk_init()
380 clk_table[i] = ERR_PTR(-ENOENT); in rockchip_clk_init()
383 ctx->clk_data.clks = clk_table; in rockchip_clk_init()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 2281 …min_dram_speed_mts = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.n… in dcn30_calculate_wm_and_dlg()
2457 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn30_update_bw_bounding_box()
2461 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn30_update_bw_bounding_box()
2462 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2463 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) in dcn30_update_bw_bounding_box()
2464 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn30_update_bw_bounding_box()
2465 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn30_update_bw_bounding_box()
2466 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn30_update_bw_bounding_box()
2467 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn30_update_bw_bounding_box()
2468 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn30_update_bw_bounding_box()
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| /drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| D | renoir_ppt.c | 180 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in renoir_get_dpm_clk_limited() local
182 if (!clk_table || clk_type >= SMU_CLK_COUNT) in renoir_get_dpm_clk_limited()
189 *freq = clk_table->SocClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
195 *freq = clk_table->FClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
200 *freq = clk_table->DcfClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
205 *freq = clk_table->FClocks[dpm_level].Freq; in renoir_get_dpm_clk_limited()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | clk_mgr.h | 209 struct clk_limit_table clk_table; member
|