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Searched refs:clock_ranges (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c919 struct pp_smu_wm_range_sets *clock_ranges) in renoir_set_watermarks_table() argument
925 if (clock_ranges) { in renoir_set_watermarks_table()
926 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in renoir_set_watermarks_table()
927 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) in renoir_set_watermarks_table()
931 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in renoir_set_watermarks_table()
933 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in renoir_set_watermarks_table()
935 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in renoir_set_watermarks_table()
937 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in renoir_set_watermarks_table()
939 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in renoir_set_watermarks_table()
942 clock_ranges->reader_wm_sets[i].wm_inst; in renoir_set_watermarks_table()
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/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dnavi10_ppt.c1617 struct pp_smu_wm_range_sets *clock_ranges) in navi10_set_watermarks_table() argument
1623 if (clock_ranges) { in navi10_set_watermarks_table()
1624 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in navi10_set_watermarks_table()
1625 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) in navi10_set_watermarks_table()
1628 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in navi10_set_watermarks_table()
1630 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in navi10_set_watermarks_table()
1632 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in navi10_set_watermarks_table()
1634 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in navi10_set_watermarks_table()
1636 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in navi10_set_watermarks_table()
1639 clock_ranges->reader_wm_sets[i].wm_inst; in navi10_set_watermarks_table()
[all …]
Dsienna_cichlid_ppt.c1448 struct pp_smu_wm_range_sets *clock_ranges) in sienna_cichlid_set_watermarks_table() argument
1454 if (clock_ranges) { in sienna_cichlid_set_watermarks_table()
1455 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || in sienna_cichlid_set_watermarks_table()
1456 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) in sienna_cichlid_set_watermarks_table()
1459 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { in sienna_cichlid_set_watermarks_table()
1461 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in sienna_cichlid_set_watermarks_table()
1463 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in sienna_cichlid_set_watermarks_table()
1465 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in sienna_cichlid_set_watermarks_table()
1467 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in sienna_cichlid_set_watermarks_table()
1470 clock_ranges->reader_wm_sets[i].wm_inst; in sienna_cichlid_set_watermarks_table()
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/drivers/gpu/drm/amd/pm/swsmu/
Dsmu_internal.h80 #define smu_set_watermarks_table(smu, clock_ranges) smu_ppt_funcs(set_watermarks_table, 0, smu, c… argument
Damdgpu_smu.c1831 struct pp_smu_wm_range_sets *clock_ranges) in smu_set_watermarks_for_clock_ranges() argument
1843 ret = smu_set_watermarks_table(smu, clock_ranges); in smu_set_watermarks_for_clock_ranges()
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dhardwaremanager.c463 void *clock_ranges) in phm_set_watermarks_for_clocks_ranges() argument
471 clock_ranges); in phm_set_watermarks_for_clocks_ranges()
Dsmu10_hwmgr.c1232 void *clock_ranges) in smu10_set_watermarks_for_clocks_ranges() argument
1235 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; in smu10_set_watermarks_for_clocks_ranges()
Dvega12_hwmgr.c1978 void *clock_ranges) in vega12_set_watermarks_for_clocks_ranges() argument
1982 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; in vega12_set_watermarks_for_clocks_ranges()
Dvega20_hwmgr.c2938 void *clock_ranges) in vega20_set_watermarks_for_clocks_ranges() argument
2942 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; in vega20_set_watermarks_for_clocks_ranges()
/drivers/gpu/drm/amd/pm/inc/
Damdgpu_smu.h505 struct pp_smu_wm_range_sets *clock_ranges);
761 struct pp_smu_wm_range_sets *clock_ranges);
Dhardwaremanager.h459 void *clock_ranges);
Dhwmgr.h310 int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
/drivers/gpu/drm/amd/include/
Dkgd_pp_interface.h308 void *clock_ranges);
/drivers/gpu/drm/amd/pm/powerplay/
Damd_powerplay.c1195 void *clock_ranges) in pp_set_watermarks_for_clocks_ranges() argument
1200 if (!hwmgr || !hwmgr->pm_en || !clock_ranges) in pp_set_watermarks_for_clocks_ranges()
1205 clock_ranges); in pp_set_watermarks_for_clocks_ranges()