Searched refs:clock_req (Results 1 – 11 of 11) sorted by relevance
| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_pp_smu.c | 728 struct pp_display_clock_request clock_req; in pp_nv_set_hard_min_dcefclk_by_freq() local
733 clock_req.clock_type = amd_pp_dcef_clock; in pp_nv_set_hard_min_dcefclk_by_freq()
734 clock_req.clock_freq_in_khz = mhz * 1000; in pp_nv_set_hard_min_dcefclk_by_freq()
739 if (smu_display_clock_voltage_request(smu, &clock_req)) in pp_nv_set_hard_min_dcefclk_by_freq()
751 struct pp_display_clock_request clock_req; in pp_nv_set_hard_min_uclk_by_freq() local
756 clock_req.clock_type = amd_pp_mem_clock; in pp_nv_set_hard_min_uclk_by_freq()
757 clock_req.clock_freq_in_khz = mhz * 1000; in pp_nv_set_hard_min_uclk_by_freq()
762 if (smu_display_clock_voltage_request(smu, &clock_req)) in pp_nv_set_hard_min_uclk_by_freq()
787 struct pp_display_clock_request clock_req; in pp_nv_set_voltage_by_freq() local
794 clock_req.clock_type = amd_pp_disp_clock; in pp_nv_set_voltage_by_freq()
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| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | smu10_hwmgr.c | 52 struct pp_display_clock_request *clock_req) in smu10_display_clock_voltage_request() argument
55 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu10_display_clock_voltage_request()
56 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; in smu10_display_clock_voltage_request()
191 struct pp_display_clock_request clock_req; in smu10_set_clock_limit() local
194 clock_req.clock_type = amd_pp_dcf_clock; in smu10_set_clock_limit()
195 clock_req.clock_freq_in_khz = clocks.dcefClock * 10; in smu10_set_clock_limit()
197 PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req), in smu10_set_clock_limit()
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| D | vega12_hwmgr.c | 1544 struct pp_display_clock_request *clock_req) in vega12_display_clock_voltage_request() argument
1548 enum amd_pp_clock_type clk_type = clock_req->clock_type; in vega12_display_clock_voltage_request()
1549 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; in vega12_display_clock_voltage_request()
1591 struct pp_display_clock_request clock_req; in vega12_notify_smc_display_config_after_ps_adjustment() local
1605 clock_req.clock_type = amd_pp_dcef_clock; in vega12_notify_smc_display_config_after_ps_adjustment()
1606 clock_req.clock_freq_in_khz = min_clocks.dcefClock/10; in vega12_notify_smc_display_config_after_ps_adjustment()
1607 if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) { in vega12_notify_smc_display_config_after_ps_adjustment()
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| D | vega20_hwmgr.c | 2288 struct pp_display_clock_request *clock_req) in vega20_display_clock_voltage_request() argument
2292 enum amd_pp_clock_type clk_type = clock_req->clock_type; in vega20_display_clock_voltage_request()
2293 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; in vega20_display_clock_voltage_request()
2344 struct pp_display_clock_request clock_req; in vega20_notify_smc_display_config_after_ps_adjustment() local
2352 clock_req.clock_type = amd_pp_dcef_clock; in vega20_notify_smc_display_config_after_ps_adjustment()
2353 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10; in vega20_notify_smc_display_config_after_ps_adjustment()
2354 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) { in vega20_notify_smc_display_config_after_ps_adjustment()
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| D | vega10_hwmgr.c | 3974 struct pp_display_clock_request *clock_req) in vega10_display_clock_voltage_request() argument
3977 enum amd_pp_clock_type clk_type = clock_req->clock_type; in vega10_display_clock_voltage_request()
3978 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; in vega10_display_clock_voltage_request()
4044 struct pp_display_clock_request clock_req; in vega10_notify_smc_display_config_after_ps_adjustment() local
4063 clock_req.clock_type = amd_pp_dcef_clock; in vega10_notify_smc_display_config_after_ps_adjustment()
4064 clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value * 10; in vega10_notify_smc_display_config_after_ps_adjustment()
4065 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) { in vega10_notify_smc_display_config_after_ps_adjustment()
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| /drivers/gpu/drm/amd/pm/inc/ |
| D | smu_v11_0.h | 194 *clock_req);
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| D | amdgpu_smu.h | 566 *clock_req);
727 struct pp_display_clock_request *clock_req);
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| /drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | smu_v11_0.c | 1013 *clock_req) in smu_v11_0_display_clock_voltage_request()
1015 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu_v11_0_display_clock_voltage_request()
1018 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; in smu_v11_0_display_clock_voltage_request()
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| D | navi10_ppt.c | 1577 struct pp_display_clock_request clock_req; in navi10_notify_smc_display_config() local
1585 clock_req.clock_type = amd_pp_dcef_clock; in navi10_notify_smc_display_config()
1586 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; in navi10_notify_smc_display_config()
1588 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); in navi10_notify_smc_display_config()
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| D | sienna_cichlid_ppt.c | 1408 struct pp_display_clock_request clock_req; in sienna_cichlid_notify_smc_display_config() local
1416 clock_req.clock_type = amd_pp_dcef_clock; in sienna_cichlid_notify_smc_display_config()
1417 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; in sienna_cichlid_notify_smc_display_config()
1419 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); in sienna_cichlid_notify_smc_display_config()
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| /drivers/gpu/drm/amd/pm/swsmu/ |
| D | amdgpu_smu.c | 2383 struct pp_display_clock_request *clock_req) in smu_display_clock_voltage_request() argument
2393 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); in smu_display_clock_voltage_request()
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