1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #ifndef __DAL_CLK_MGR_INTERNAL_H__
27 #define __DAL_CLK_MGR_INTERNAL_H__
28
29 #include "clk_mgr.h"
30 #include "dc.h"
31
32 /*
33 * only thing needed from here is MEMORY_TYPE_MULTIPLIER_CZ, which is also
34 * used in resource, perhaps this should be defined somewhere more common.
35 */
36 #include "resource.h"
37
38
39 /* Starting DID for each range */
40 enum dentist_base_divider_id {
41 DENTIST_BASE_DID_1 = 0x08,
42 DENTIST_BASE_DID_2 = 0x40,
43 DENTIST_BASE_DID_3 = 0x60,
44 DENTIST_BASE_DID_4 = 0x7e,
45 DENTIST_MAX_DID = 0x7f
46 };
47
48 /* Starting point and step size for each divider range.*/
49 enum dentist_divider_range {
50 DENTIST_DIVIDER_RANGE_1_START = 8, /* 2.00 */
51 DENTIST_DIVIDER_RANGE_1_STEP = 1, /* 0.25 */
52 DENTIST_DIVIDER_RANGE_2_START = 64, /* 16.00 */
53 DENTIST_DIVIDER_RANGE_2_STEP = 2, /* 0.50 */
54 DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */
55 DENTIST_DIVIDER_RANGE_3_STEP = 4, /* 1.00 */
56 DENTIST_DIVIDER_RANGE_4_START = 248, /* 62.00 */
57 DENTIST_DIVIDER_RANGE_4_STEP = 264, /* 66.00 */
58 DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4
59 };
60
61 /*
62 ***************************************************************************************
63 ****************** Clock Manager Private Macros and Defines ***************************
64 ***************************************************************************************
65 */
66
67 /* Macros */
68
69 #define TO_CLK_MGR_INTERNAL(clk_mgr)\
70 container_of(clk_mgr, struct clk_mgr_internal, base)
71
72 #define CTX \
73 clk_mgr->base.ctx
74
75 #define DC_LOGGER \
76 clk_mgr->base.ctx->logger
77
78
79
80
81 #define CLK_BASE(inst) \
82 CLK_BASE_INNER(inst)
83
84 #define CLK_SRI(reg_name, block, inst)\
85 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
86 mm ## block ## _ ## inst ## _ ## reg_name
87
88 #define CLK_COMMON_REG_LIST_DCE_BASE() \
89 .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
90 .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL
91
92 #if defined(CONFIG_DRM_AMD_DC_SI)
93 #define CLK_COMMON_REG_LIST_DCE60_BASE() \
94 SR(DENTIST_DISPCLK_CNTL)
95 #endif
96
97 #define CLK_COMMON_REG_LIST_DCN_BASE() \
98 SR(DENTIST_DISPCLK_CNTL)
99
100 #define VBIOS_SMU_MSG_BOX_REG_LIST_RV() \
101 .MP1_SMN_C2PMSG_91 = mmMP1_SMN_C2PMSG_91, \
102 .MP1_SMN_C2PMSG_83 = mmMP1_SMN_C2PMSG_83, \
103 .MP1_SMN_C2PMSG_67 = mmMP1_SMN_C2PMSG_67
104
105 #define CLK_REG_LIST_NV10() \
106 SR(DENTIST_DISPCLK_CNTL), \
107 CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \
108 CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)
109
110 #ifdef CONFIG_DRM_AMD_DC_DCN3_0
111 // TODO:
112 #define CLK_REG_LIST_DCN3() \
113 SR(DENTIST_DISPCLK_CNTL)
114 #endif
115
116 #define CLK_SF(reg_name, field_name, post_fix)\
117 .field_name = reg_name ## __ ## field_name ## post_fix
118
119 #define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
120 CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
121 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh)
122
123 #if defined(CONFIG_DRM_AMD_DC_SI)
124 #define CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh) \
125 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
126 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
127 #endif
128
129 #define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
130 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
131 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
132
133 #define CLK_MASK_SH_LIST_RV1(mask_sh) \
134 CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
135 CLK_SF(MP1_SMN_C2PMSG_67, CONTENT, mask_sh),\
136 CLK_SF(MP1_SMN_C2PMSG_83, CONTENT, mask_sh),\
137 CLK_SF(MP1_SMN_C2PMSG_91, CONTENT, mask_sh),
138
139 #define CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh) \
140 CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
141 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\
142 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh)
143
144 #define CLK_MASK_SH_LIST_NV10(mask_sh) \
145 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
146 CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_int, mask_sh),\
147 CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_frac, mask_sh)
148
149 #define CLK_REG_FIELD_LIST(type) \
150 type DPREFCLK_SRC_SEL; \
151 type DENTIST_DPREFCLK_WDIVIDER; \
152 type DENTIST_DISPCLK_WDIVIDER; \
153 type DENTIST_DISPCLK_CHG_DONE;
154
155 /*
156 ***************************************************************************************
157 ****************** Clock Manager Private Structures ***********************************
158 ***************************************************************************************
159 */
160 #define CLK20_REG_FIELD_LIST(type) \
161 type DENTIST_DPPCLK_WDIVIDER; \
162 type DENTIST_DPPCLK_CHG_DONE; \
163 type FbMult_int; \
164 type FbMult_frac;
165
166 #define VBIOS_SMU_REG_FIELD_LIST(type) \
167 type CONTENT;
168
169 struct clk_mgr_shift {
170 CLK_REG_FIELD_LIST(uint8_t)
171 CLK20_REG_FIELD_LIST(uint8_t)
172 VBIOS_SMU_REG_FIELD_LIST(uint32_t)
173 };
174
175 struct clk_mgr_mask {
176 CLK_REG_FIELD_LIST(uint32_t)
177 CLK20_REG_FIELD_LIST(uint32_t)
178 VBIOS_SMU_REG_FIELD_LIST(uint32_t)
179 };
180
181 struct clk_mgr_registers {
182 uint32_t DPREFCLK_CNTL;
183 uint32_t DENTIST_DISPCLK_CNTL;
184
185 uint32_t CLK3_CLK2_DFS_CNTL;
186 uint32_t CLK3_CLK_PLL_REQ;
187
188 #ifdef CONFIG_DRM_AMD_DC_DCN3_0
189 uint32_t CLK0_CLK2_DFS_CNTL;
190 uint32_t CLK0_CLK_PLL_REQ;
191 #endif
192 uint32_t MP1_SMN_C2PMSG_67;
193 uint32_t MP1_SMN_C2PMSG_83;
194 uint32_t MP1_SMN_C2PMSG_91;
195 };
196
197 enum clock_type {
198 clock_type_dispclk = 1,
199 clock_type_dcfclk,
200 clock_type_socclk,
201 clock_type_pixelclk,
202 clock_type_phyclk,
203 clock_type_dppclk,
204 clock_type_fclk,
205 clock_type_dcfdsclk,
206 clock_type_dscclk,
207 clock_type_uclk,
208 clock_type_dramclk,
209 };
210
211
212 struct state_dependent_clocks {
213 int display_clk_khz;
214 int pixel_clk_khz;
215 };
216
217 struct clk_mgr_internal {
218 struct clk_mgr base;
219 int smu_ver;
220 struct pp_smu_funcs *pp_smu;
221 struct clk_mgr_internal_funcs *funcs;
222
223 struct dccg *dccg;
224
225 /*
226 * For backwards compatbility with previous implementation
227 * TODO: remove these after everything transitions to new pattern
228 * Rationale is that clk registers change a lot across DCE versions
229 * and a shared data structure doesn't really make sense.
230 */
231 const struct clk_mgr_registers *regs;
232 const struct clk_mgr_shift *clk_mgr_shift;
233 const struct clk_mgr_mask *clk_mgr_mask;
234
235 struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
236
237 /*TODO: figure out which of the below fields should be here vs in asic specific portion */
238 /* Cache the status of DFS-bypass feature*/
239 bool dfs_bypass_enabled;
240 /* True if the DFS-bypass feature is enabled and active. */
241 bool dfs_bypass_active;
242
243 uint32_t dfs_ref_freq_khz;
244 /*
245 * Cache the display clock returned by VBIOS if DFS-bypass is enabled.
246 * This is basically "Crystal Frequency In KHz" (XTALIN) frequency
247 */
248 int dfs_bypass_disp_clk;
249
250 /**
251 * @ss_on_dprefclk:
252 *
253 * True if spread spectrum is enabled on the DP ref clock.
254 */
255 bool ss_on_dprefclk;
256
257 /**
258 * @xgmi_enabled:
259 *
260 * True if xGMI is enabled. On VG20, both audio and display clocks need
261 * to be adjusted with the WAFL link's SS info if xGMI is enabled.
262 */
263 bool xgmi_enabled;
264
265 /**
266 * @dprefclk_ss_percentage:
267 *
268 * DPREFCLK SS percentage (if down-spread enabled).
269 *
270 * Note that if XGMI is enabled, the SS info (percentage and divider)
271 * from the WAFL link is used instead. This is decided during
272 * dce_clk_mgr initialization.
273 */
274 int dprefclk_ss_percentage;
275
276 /**
277 * @dprefclk_ss_divider:
278 *
279 * DPREFCLK SS percentage Divider (100 or 1000).
280 */
281 int dprefclk_ss_divider;
282
283 enum dm_pp_clocks_state max_clks_state;
284 enum dm_pp_clocks_state cur_min_clks_state;
285 bool periodic_retraining_disabled;
286
287 unsigned int cur_phyclk_req_table[MAX_PIPES * 2];
288 #ifdef CONFIG_DRM_AMD_DC_DCN3_0
289
290 bool smu_present;
291 void *wm_range_table;
292 long long wm_range_table_addr;
293 #endif
294 };
295
296 struct clk_mgr_internal_funcs {
297 int (*set_dispclk)(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
298 int (*set_dprefclk)(struct clk_mgr_internal *clk_mgr);
299 };
300
301
302 /*
303 ***************************************************************************************
304 ****************** Clock Manager Level Helper functions *******************************
305 ***************************************************************************************
306 */
307
308
should_set_clock(bool safe_to_lower,int calc_clk,int cur_clk)309 static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk)
310 {
311 return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk);
312 }
313
should_update_pstate_support(bool safe_to_lower,bool calc_support,bool cur_support)314 static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support)
315 {
316 if (cur_support != calc_support) {
317 if (calc_support == true && safe_to_lower)
318 return true;
319 else if (calc_support == false && !safe_to_lower)
320 return true;
321 }
322
323 return false;
324 }
325
326 int clk_mgr_helper_get_active_display_cnt(
327 struct dc *dc,
328 struct dc_state *context);
329
330 int clk_mgr_helper_get_active_plane_cnt(
331 struct dc *dc,
332 struct dc_state *context);
333
334
335
336 #endif //__DAL_CLK_MGR_INTERNAL_H__
337