Searched refs:cps (Results 1 – 13 of 13) sorted by relevance
| /drivers/cpuidle/ |
| D | Makefile | 31 obj-$(CONFIG_MIPS_CPS_CPUIDLE) += cpuidle-cps.o
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| /drivers/atm/ |
| D | idt77252.c | 729 u32 cps = vc->estimator->maxcps; in push_on_scq() local
731 vc->estimator->cps = cps; in push_on_scq()
732 vc->estimator->avcps = cps << 5; in push_on_scq()
2082 u32 rate, cps; in idt77252_est_timer() local
2094 est->cps = (est->avcps + 0x1f) >> 5; in idt77252_est_timer()
2096 cps = est->cps; in idt77252_est_timer()
2097 if (cps < (est->maxcps >> 4)) in idt77252_est_timer()
2098 cps = est->maxcps >> 4; in idt77252_est_timer()
2100 lacr = idt77252_rate_logindex(card, cps); in idt77252_est_timer()
2125 est->cps = est->maxcps; in idt77252_init_est()
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| D | iphase.c | 342 u32 exp, mantissa, cps;
349 cps = (1 << M_BITS) | mantissa;
351 cps = cps;
353 cps <<= (exp - M_BITS);
355 cps >>= (M_BITS - exp);
356 return cps;
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| D | idt77252.h | 196 u32 cps; member
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| /drivers/staging/fwserial/ |
| D | fwserial.h | 250 unsigned int cps; member
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| D | fwserial.c | 507 n = (elapsed * port->cps) / HZ + 1; in fwtty_emit_breaks()
950 port->cps = (baud << 1) / frame; in set_termios()
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| /drivers/gpu/drm/amd/pm/inc/ |
| D | amdgpu_dpm.h | 331 #define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \ argument
332 …((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal)))
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| /drivers/gpu/drm/amd/include/ |
| D | kgd_pp_interface.h | 246 void *cps,
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| /drivers/gpu/drm/amd/pm/powerplay/ |
| D | kv_dpm.c | 3231 struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps; in kv_check_state_equal() local
3235 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) in kv_check_state_equal()
3238 kv_cps = kv_get_ps(cps); in kv_check_state_equal()
3260 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); in kv_check_state_equal()
3261 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); in kv_check_state_equal()
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| D | si_dpm.c | 7944 struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps; in si_check_state_equal() local
7948 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) in si_check_state_equal()
7951 si_cps = si_get_ps((struct amdgpu_ps *)cps); in si_check_state_equal()
7974 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); in si_check_state_equal()
7975 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); in si_check_state_equal()
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| /drivers/tty/ |
| D | rocket.c | 750 info->cps = baud / bits; in configure_r_port()
986 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps; in rp_close()
1435 printk(KERN_INFO "cps=%d...\n", info->cps); in rp_wait_until_sent()
1442 check_time = (HZ / info->cps) / 5; in rp_wait_until_sent()
1444 check_time = HZ * txcnt / info->cps; in rp_wait_until_sent()
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| D | rocket_int.h | 1146 int cps; member
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| /drivers/block/drbd/ |
| D | drbd_worker.c | 507 int cps; /* correction per invocation of drbd_rs_controller() */ in drbd_rs_controller() local
528 cps = correction / steps; in drbd_rs_controller()
529 fifo_add_val(plan, cps); in drbd_rs_controller()
530 plan->total += cps * steps; in drbd_rs_controller()
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