Home
last modified time | relevance | path

Searched refs:cw6 (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_dcn30.c123 const struct dmub_window *cw6) in dmub_dcn30_setup_windows() argument
182 offset = cw6->offset; in dmub_dcn30_setup_windows()
186 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); in dmub_dcn30_setup_windows()
188 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, in dmub_dcn30_setup_windows()
Ddmub_dcn20.c182 const struct dmub_window *cw6) in dmub_dcn20_setup_windows() argument
244 dmub_dcn20_translate_addr(&cw6->offset, fb_base, fb_offset, &offset); in dmub_dcn20_setup_windows()
248 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); in dmub_dcn20_setup_windows()
250 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, in dmub_dcn20_setup_windows()
Ddmub_srv.c404 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; in dmub_srv_hw_init() local
458 cw6.offset.quad_part = fw_state_fb->gpu_addr; in dmub_srv_hw_init()
459 cw6.region.base = DMUB_CW6_BASE; in dmub_srv_hw_init()
460 cw6.region.top = cw6.region.base + fw_state_fb->size; in dmub_srv_hw_init()
468 &cw5, &cw6); in dmub_srv_hw_init()
Ddmub_dcn30.h46 const struct dmub_window *cw6);
Ddmub_dcn20.h174 const struct dmub_window *cw6);
/drivers/gpu/drm/amd/display/dmub/
Ddmub_srv.h256 const struct dmub_window *cw6);