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Searched refs:dcfclk (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/display/dc/inc/hw/
Dclk_mgr.h129 uint32_t dcfclk; member
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calc_auto.c1006 v->dcfclk = v->dcfclk_per_state[v->voltage_level]; in mode_support_and_system_configuration()
1226 …v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwi… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1234 …if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_b… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1235 …->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_wi… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1237 …v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_b… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1239 …byte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk * v->urgent_latenc… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1241 …v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwi… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1242 …if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_b… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1243 …->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_wi… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1245 …v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_b… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
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Ddcn_calcs.c494 input->clks_cfg.dcfclk_mhz = v->dcfclk; in dcn_bw_calc_rq_dlg_ttu()
578 v->dcfclk = v->dcfclkv_nom0p8;
599 v->dcfclk = v->dcfclkv_max0p9;
619 v->dcfclk = v->dcfclk_per_state[v->voltage_level];
1181 context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000); in dcn_validate_bandwidth()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr.c275 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; in rn_dump_clk_registers()
302 regs_and_bypass->dcfclk, in rn_dump_clk_registers()
/drivers/gpu/drm/amd/display/dc/inc/
Ddcn_calcs.h213 float dcfclk; member
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_resource.c2212 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn30_calculate_wm_and_dlg() local
2216 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) in dcn30_calculate_wm_and_dlg()
2217 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; in dcn30_calculate_wm_and_dlg()
2220 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_calculate_wm_and_dlg()
2246 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_calculate_wm_and_dlg()