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Searched refs:dcfclk_mhz (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c168 .dcfclk_mhz = 400.0,
179 .dcfclk_mhz = 464.52,
190 .dcfclk_mhz = 514.29,
201 .dcfclk_mhz = 576.00,
212 .dcfclk_mhz = 626.09,
223 .dcfclk_mhz = 685.71,
234 .dcfclk_mhz = 757.89,
245 .dcfclk_mhz = 847.06,
257 .dcfclk_mhz = 847.06,
1038 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
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/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr.c448 …der_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in build_watermark_ranges()
450 …ges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in build_watermark_ranges()
551 .dcfclk_mhz = 400,
558 .dcfclk_mhz = 483,
565 .dcfclk_mhz = 602,
572 .dcfclk_mhz = 738,
811 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FCl… in rn_clk_mgr_helper_populate_bw_params()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c233 .dcfclk_mhz = 560.0,
244 .dcfclk_mhz = 694.0,
255 .dcfclk_mhz = 875.0,
266 .dcfclk_mhz = 1000.0,
277 .dcfclk_mhz = 1200.0,
289 .dcfclk_mhz = 1200.0,
344 .dcfclk_mhz = 560.0,
355 .dcfclk_mhz = 694.0,
366 .dcfclk_mhz = 875.0,
377 .dcfclk_mhz = 1000.0,
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/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_resource.c1808 dcn3_0_soc.clock_limits[i].dcfclk_mhz = in init_soc_bounding_box()
1809 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz); in init_soc_bounding_box()
2220 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_calculate_wm_and_dlg()
2230 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; in dcn30_calculate_wm_and_dlg()
2246 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_calculate_wm_and_dlg()
2439 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box() local
2461 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn30_update_bw_bounding_box()
2462 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2472 max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2502 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { in dcn30_update_bw_bounding_box()
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/drivers/gpu/drm/amd/amdgpu/
Damdgpu_socbb.h29 uint32_t dcfclk_mhz; member
/drivers/gpu/drm/amd/display/dc/dml/
Ddisplay_mode_structs.h60 double dcfclk_mhz; member
370 double dcfclk_mhz; member
Ddisplay_mode_lib.c248 dml_print("DML PARAMS: dcfclk_mhz = %3.2f\n", clks_cfg->dcfclk_mhz); in dml_log_pipe_params()
Ddisplay_mode_vba.c249 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
264 mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
844 mode_lib->vba.DCFCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dcfclk_mhz; in ModeSupportAndSystemConfiguration()
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dclk_mgr.h73 unsigned int dcfclk_mhz; member
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr.c175 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks()
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c494 input->clks_cfg.dcfclk_mhz = v->dcfclk; in dcn_bw_calc_rq_dlg_ttu()