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Searched refs:ddb_y (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_pm.h40 struct skl_ddb_entry *ddb_y,
Dintel_pm.c4302 struct skl_ddb_entry *ddb_y, in skl_ddb_get_hw_plane_state() argument
4311 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val); in skl_ddb_get_hw_plane_state()
4325 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val); in skl_ddb_get_hw_plane_state()
4334 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val); in skl_ddb_get_hw_plane_state()
4340 struct skl_ddb_entry *ddb_y, in skl_pipe_ddb_get_hw_state() argument
4357 &ddb_y[plane_id], in skl_pipe_ddb_get_hw_state()
5654 const struct skl_ddb_entry *ddb_y = in skl_write_plane_wm() local
5672 PLANE_BUF_CFG(pipe, plane_id), ddb_y); in skl_write_plane_wm()
5677 swap(ddb_y, ddb_uv); in skl_write_plane_wm()
5680 PLANE_BUF_CFG(pipe, plane_id), ddb_y); in skl_write_plane_wm()
/drivers/gpu/drm/i915/display/
Dintel_display.c14086 struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; in verify_wm_state() member
14106 skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv); in verify_wm_state()
14157 hw_ddb_entry = &hw->ddb_y[plane]; in verify_wm_state()
14214 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR]; in verify_wm_state()