| /drivers/clk/baikal-t1/ |
| D | ccu-div.c | 62 unsigned long div) in ccu_div_lock_delay_ns() argument
64 u64 ns = 4ULL * (div ?: 1) * NSEC_PER_SEC; in ccu_div_lock_delay_ns()
72 unsigned long div) in ccu_div_calc_freq() argument
74 return ref_clk / (div ?: 1); in ccu_div_calc_freq()
77 static int ccu_div_var_update_clkdiv(struct ccu_div *div, in ccu_div_var_update_clkdiv() argument
88 if (div->features & CCU_DIV_LOCK_SHIFTED) in ccu_div_var_update_clkdiv()
93 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_var_update_clkdiv()
103 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_var_update_clkdiv()
114 struct ccu_div *div = to_ccu_div(hw); in ccu_div_var_enable() local
124 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_var_enable()
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| /drivers/clk/berlin/ |
| D | berlin2-div.c | 67 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_is_enabled() local
68 struct berlin2_div_map *map = &div->map; in berlin2_div_is_enabled()
71 if (div->lock) in berlin2_div_is_enabled()
72 spin_lock(div->lock); in berlin2_div_is_enabled()
74 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_is_enabled()
77 if (div->lock) in berlin2_div_is_enabled()
78 spin_unlock(div->lock); in berlin2_div_is_enabled()
85 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_enable() local
86 struct berlin2_div_map *map = &div->map; in berlin2_div_enable()
89 if (div->lock) in berlin2_div_enable()
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| /drivers/clk/ |
| D | clk-divider.c | 50 for (clkt = table; clkt->div; clkt++) in _get_table_maxdiv()
51 if (clkt->div > maxdiv && clkt->val <= mask) in _get_table_maxdiv()
52 maxdiv = clkt->div; in _get_table_maxdiv()
61 for (clkt = table; clkt->div; clkt++) in _get_table_mindiv()
62 if (clkt->div < mindiv) in _get_table_mindiv()
63 mindiv = clkt->div; in _get_table_mindiv()
84 for (clkt = table; clkt->div; clkt++) in _get_table_div()
86 return clkt->div; in _get_table_div()
105 unsigned int div) in _get_table_val() argument
109 for (clkt = table; clkt->div; clkt++) in _get_table_val()
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| D | clk-milbeaut.c | 83 u8 div; member
101 { .val = 0, .div = 8 },
102 { .val = 1, .div = 9 },
103 { .val = 2, .div = 10 },
104 { .val = 3, .div = 15 },
105 { .div = 0 },
109 { .val = 1, .div = 2 },
110 { .val = 3, .div = 4 },
111 { .div = 0 },
115 { .val = 3, .div = 4 },
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| D | clk-cdce706.c | 29 #define CDCE706_DIVIDER(div) (13 + (div)) argument
50 #define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4)) argument
51 #define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1)) argument
52 #define CDCE706_DIVIDER_PLL_MASK(div) (0x7 << CDCE706_DIVIDER_PLL_SHIFT(div)) argument
72 unsigned div; member
169 __func__, hwd->idx, hwd->mux, hwd->mul, hwd->div); in cdce706_pll_recalc_rate()
172 if (hwd->div && hwd->mul) { in cdce706_pll_recalc_rate()
175 do_div(res, hwd->div); in cdce706_pll_recalc_rate()
179 if (hwd->div) in cdce706_pll_recalc_rate()
180 return parent_rate / hwd->div; in cdce706_pll_recalc_rate()
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| /drivers/clk/ti/ |
| D | divider.c | 34 for (clkt = table; clkt->div; clkt++) in _get_table_div()
36 return clkt->div; in _get_table_div()
49 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
80 unsigned int div) in _get_table_val() argument
84 for (clkt = table; clkt->div; clkt++) in _get_table_val()
85 if (clkt->div == div) in _get_table_val()
90 static unsigned int _get_val(struct clk_omap_divider *divider, u8 div) in _get_val() argument
93 return div; in _get_val()
95 return __ffs(div); in _get_val()
97 return _get_table_val(divider->table, div); in _get_val()
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| /drivers/clk/imx/ |
| D | clk-divider-gate.c | 21 struct clk_divider *div = to_clk_divider(hw); in to_clk_divider_gate() local
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
29 struct clk_divider *div = to_clk_divider(hw); in clk_divider_gate_recalc_rate_ro() local
32 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate_ro()
33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro()
37 return divider_recalc_rate(hw, parent_rate, val, div->table, in clk_divider_gate_recalc_rate_ro()
38 div->flags, div->width); in clk_divider_gate_recalc_rate_ro()
45 struct clk_divider *div = to_clk_divider(hw); in clk_divider_gate_recalc_rate() local
49 spin_lock_irqsave(div->lock, flags); in clk_divider_gate_recalc_rate()
54 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate()
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| /drivers/clk/sunxi/ |
| D | clk-sunxi.c | 35 u8 div; in sun4i_get_pll1_factors() local
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
52 if (div < 10) in sun4i_get_pll1_factors()
56 else if (div < 20 || (div < 32 && (div & 1))) in sun4i_get_pll1_factors()
61 else if (div < 40 || (div < 64 && (div & 2))) in sun4i_get_pll1_factors()
69 div <<= req->p; in sun4i_get_pll1_factors()
70 div /= (req->k + 1); in sun4i_get_pll1_factors()
71 req->n = div / 4; in sun4i_get_pll1_factors()
159 u8 div; in sun8i_a23_get_pll1_factors() local
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| D | clk-sun9i-cpus.c | 36 #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ argument
37 (div << SUN9I_CPUS_DIV_SHIFT))
42 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ argument
43 (div << SUN9I_CPUS_PLL4_DIV_SHIFT))
75 u8 div, pre_div = 1; in sun9i_a80_cpus_clk_round() local
84 div = DIV_ROUND_UP(parent_rate, rate); in sun9i_a80_cpus_clk_round()
87 if (parent == SUN9I_CPUS_MUX_PARENT_PLL4 && div > 4) { in sun9i_a80_cpus_clk_round()
89 if (div < 32) { in sun9i_a80_cpus_clk_round()
90 pre_div = div; in sun9i_a80_cpus_clk_round()
91 div = 1; in sun9i_a80_cpus_clk_round()
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| /drivers/clk/mxs/ |
| D | clk-div.c | 38 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate() local
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
46 struct clk_div *div = to_clk_div(hw); in clk_div_round_rate() local
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
54 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate() local
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
59 ret = mxs_clk_wait(div->reg, div->busy); in clk_div_set_rate()
73 struct clk_div *div; in mxs_clk_div() local
77 div = kzalloc(sizeof(*div), GFP_KERNEL); in mxs_clk_div()
78 if (!div) in mxs_clk_div()
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| /drivers/clk/bcm/ |
| D | clk-iproc-asiu.c | 32 struct iproc_asiu_div div; member
92 val = readl(asiu->div_base + clk->div.offset); in iproc_asiu_clk_recalc_rate()
93 if ((val & (1 << clk->div.en_shift)) == 0) { in iproc_asiu_clk_recalc_rate()
99 div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width); in iproc_asiu_clk_recalc_rate()
101 div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width); in iproc_asiu_clk_recalc_rate()
114 unsigned int div; in iproc_asiu_clk_round_rate() local
122 div = DIV_ROUND_CLOSEST(*parent_rate, rate); in iproc_asiu_clk_round_rate()
123 if (div < 2) in iproc_asiu_clk_round_rate()
126 return *parent_rate / div; in iproc_asiu_clk_round_rate()
134 unsigned int div, div_h, div_l; in iproc_asiu_clk_set_rate() local
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| D | clk-kona.c | 58 static inline u64 scaled_div_value(struct bcm_clk_div *div, u32 reg_div) in scaled_div_value() argument
60 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
68 u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, u32 billionths) in scaled_div_build() argument
76 combined <<= div->u.s.frac_width; in scaled_div_build()
83 scaled_div_min(struct bcm_clk_div *div) in scaled_div_min() argument
85 if (divider_is_fixed(div)) in scaled_div_min()
86 return (u64)div->u.fixed; in scaled_div_min()
88 return scaled_div_value(div, 0); in scaled_div_min()
92 u64 scaled_div_max(struct bcm_clk_div *div) in scaled_div_max() argument
96 if (divider_is_fixed(div)) in scaled_div_max()
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| /drivers/clk/meson/ |
| D | clk-regmap.c | 63 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); in clk_regmap_div_recalc_rate() local
67 ret = regmap_read(clk->map, div->offset, &val); in clk_regmap_div_recalc_rate()
72 val >>= div->shift; in clk_regmap_div_recalc_rate()
73 val &= clk_div_mask(div->width); in clk_regmap_div_recalc_rate()
74 return divider_recalc_rate(hw, prate, val, div->table, div->flags, in clk_regmap_div_recalc_rate()
75 div->width); in clk_regmap_div_recalc_rate()
82 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); in clk_regmap_div_round_rate() local
87 if (div->flags & CLK_DIVIDER_READ_ONLY) { in clk_regmap_div_round_rate()
88 ret = regmap_read(clk->map, div->offset, &val); in clk_regmap_div_round_rate()
93 val >>= div->shift; in clk_regmap_div_round_rate()
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| /drivers/mmc/host/ |
| D | meson-mx-sdhc-clkc.c | 19 struct clk_divider div; member
34 { .div = 6, .val = 5, },
35 { .div = 8, .val = 7, },
36 { .div = 9, .val = 8, },
37 { .div = 10, .val = 9, },
38 { .div = 12, .val = 11, },
39 { .div = 16, .val = 15, },
40 { .div = 18, .val = 17, },
41 { .div = 34, .val = 33, },
42 { .div = 142, .val = 141, },
[all …]
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| /drivers/clk/ingenic/ |
| D | cgu.c | 371 u32 div_reg, div; in ingenic_clk_recalc_rate() local
374 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
375 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
376 GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_recalc_rate()
378 if (clk_info->div.div_table) in ingenic_clk_recalc_rate()
379 div = clk_info->div.div_table[div]; in ingenic_clk_recalc_rate()
381 div = (div + 1) * clk_info->div.div; in ingenic_clk_recalc_rate()
383 rate /= div; in ingenic_clk_recalc_rate()
385 rate /= clk_info->fixdiv.div; in ingenic_clk_recalc_rate()
393 unsigned int div) in ingenic_clk_calc_hw_div() argument
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| /drivers/clk/tegra/ |
| D | clk-divider.c | 24 int div; in get_div() local
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
29 if (div < 0) in get_div()
32 return div; in get_div()
40 int div, mul; in clk_frac_div_recalc_rate() local
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
52 div += mul; in clk_frac_div_recalc_rate()
55 rate += div - 1; in clk_frac_div_recalc_rate()
56 do_div(rate, div); in clk_frac_div_recalc_rate()
65 int div, mul; in clk_frac_div_round_rate() local
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| /drivers/clk/zynqmp/ |
| D | divider.c | 85 u32 div, value; in zynqmp_clk_divider_recalc_rate() local
88 ret = zynqmp_pm_clock_getdivider(clk_id, &div); in zynqmp_clk_divider_recalc_rate()
95 value = div & 0xFFFF; in zynqmp_clk_divider_recalc_rate()
97 value = div >> 16; in zynqmp_clk_divider_recalc_rate()
175 u32 value, div; in zynqmp_clk_divider_set_rate() local
180 div = value & 0xFFFF; in zynqmp_clk_divider_set_rate()
181 div |= 0xffff << 16; in zynqmp_clk_divider_set_rate()
183 div = 0xffff; in zynqmp_clk_divider_set_rate()
184 div |= value << 16; in zynqmp_clk_divider_set_rate()
188 div = __ffs(div); in zynqmp_clk_divider_set_rate()
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| /drivers/clk/spear/ |
| D | spear1340_clock.c | 191 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */
192 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
193 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
194 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
195 {.div = 0x03031}, /* for vco1div2 = 250 MHz */
196 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
243 {.div = 0x08000},
244 {.div = 0x06a38},
245 {.div = 0x06666},
246 {.div = 0x06000},
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| /drivers/clk/x86/ |
| D | clk-cgu.c | 165 struct lgm_clk_divider *div = to_lgm_clk_divider(hw); in lgm_clk_divider_enable_disable() local
167 if (div->flags != DIV_CLK_NO_MASK) in lgm_clk_divider_enable_disable()
168 lgm_set_clk_val(div->membase, div->reg, div->shift_gate, in lgm_clk_divider_enable_disable()
169 div->width_gate, enable); in lgm_clk_divider_enable_disable()
197 struct lgm_clk_divider *div; in lgm_clk_register_divider() local
207 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); in lgm_clk_register_divider()
208 if (!div) in lgm_clk_register_divider()
217 div->membase = ctx->membase; in lgm_clk_register_divider()
218 div->reg = reg; in lgm_clk_register_divider()
219 div->shift = shift; in lgm_clk_register_divider()
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| /drivers/media/platform/sti/hva/ |
| D | hva-debugfs.c | 121 u64 div; in hva_dbg_perf_begin() local
131 div = (u64)ktime_us_delta(dbg->begin, prev); in hva_dbg_perf_begin()
132 do_div(div, 100); in hva_dbg_perf_begin()
133 period = (u32)div; in hva_dbg_perf_begin()
152 div = (u64)dbg->window_stream_size * 80; in hva_dbg_perf_begin()
153 do_div(div, dbg->window_duration); in hva_dbg_perf_begin()
154 bitrate = (u32)div; in hva_dbg_perf_begin()
178 u64 div; in hva_dbg_perf_end() local
187 div = stream->vbuf.vb2_buf.timestamp; in hva_dbg_perf_end()
188 do_div(div, 1000); in hva_dbg_perf_end()
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| /drivers/clk/sprd/ |
| D | div.c | 13 const struct sprd_div_internal *div, in sprd_div_helper_round_rate() argument
18 NULL, div->width, 0); in sprd_div_helper_round_rate()
27 return sprd_div_helper_round_rate(&cd->common, &cd->div, in sprd_div_round_rate()
32 const struct sprd_div_internal *div, in sprd_div_helper_recalc_rate() argument
39 val = reg >> div->shift; in sprd_div_helper_recalc_rate()
40 val &= (1 << div->width) - 1; in sprd_div_helper_recalc_rate()
43 div->width); in sprd_div_helper_recalc_rate()
52 return sprd_div_helper_recalc_rate(&cd->common, &cd->div, parent_rate); in sprd_div_recalc_rate()
56 const struct sprd_div_internal *div, in sprd_div_helper_set_rate() argument
64 div->width, 0); in sprd_div_helper_set_rate()
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| /drivers/clk/qcom/ |
| D | clk-regmap-mux-div.c | 23 int mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div) in mux_div_set_src_div() argument
29 val = (div << md->hid_shift) | (src << md->src_shift); in mux_div_set_src_div()
60 u32 *div) in mux_div_get_src_div() argument
79 *div = d; in mux_div_get_src_div()
92 unsigned int i, div, max_div; in mux_div_determine_rate() local
101 for (div = 1; div < max_div; div++) { in mux_div_determine_rate()
102 parent_rate = mult_frac(req_rate, div, 2); in mux_div_determine_rate()
104 actual_rate = mult_frac(parent_rate, 2, div); in mux_div_determine_rate()
129 u32 div, max_div, best_src = 0, best_div = 0; in __mux_div_set_rate_and_parent() local
138 for (div = 1; div < max_div; div++) { in __mux_div_set_rate_and_parent()
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| /drivers/clk/at91/ |
| D | clk-master.c | 45 u8 div; member
79 u8 div; in clk_master_recalc_rate() local
91 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; in clk_master_recalc_rate()
98 rate /= characteristics->divisors[div]; in clk_master_recalc_rate()
171 return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div)); in clk_sama7g5_master_recalc_rate()
179 u32 div) in clk_sama7g5_master_best_diff() argument
183 if (div == MASTER_PRES_MAX) in clk_sama7g5_master_best_diff()
186 tmp_rate = parent_rate >> div; in clk_sama7g5_master_best_diff()
206 unsigned int div, i; in clk_sama7g5_master_determine_rate() local
218 for (div = 0; div < MASTER_PRES_MAX + 1; div++) { in clk_sama7g5_master_determine_rate()
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| /drivers/clk/actions/ |
| D | owl-factor.c | 22 for (clkt = table; clkt->div; clkt++) in _get_table_maxval()
29 unsigned int val, unsigned int *mul, unsigned int *div) in _get_table_div_mul() argument
33 for (clkt = table; clkt->div; clkt++) { in _get_table_div_mul()
36 *div = clkt->div; in _get_table_div_mul()
51 for (clkt = table; clkt->div; clkt++) { in _get_table_val()
53 do_div(calc_rate, clkt->div); in _get_table_val()
85 for (clkt = factor_hw->table; clkt->div; clkt++) { in owl_clk_val_best()
86 try_parent_rate = rate * clkt->div / clkt->mul; in owl_clk_val_best()
90 __func__, clkt->val, clkt->mul, clkt->div, in owl_clk_val_best()
103 cur_rate = DIV_ROUND_UP(parent_rate, clkt->div) * clkt->mul; in owl_clk_val_best()
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| /drivers/clk/hisilicon/ |
| D | clkdivider-hi6220.c | 104 struct hi6220_clk_divider *div; in hi6220_register_clkdiv() local
112 div = kzalloc(sizeof(*div), GFP_KERNEL); in hi6220_register_clkdiv()
113 if (!div) in hi6220_register_clkdiv()
122 kfree(div); in hi6220_register_clkdiv()
127 table[i].div = min_div + i; in hi6220_register_clkdiv()
128 table[i].val = table[i].div - 1; in hi6220_register_clkdiv()
138 div->reg = reg; in hi6220_register_clkdiv()
139 div->shift = shift; in hi6220_register_clkdiv()
140 div->width = width; in hi6220_register_clkdiv()
141 div->mask = mask_bit ? BIT(mask_bit) : 0; in hi6220_register_clkdiv()
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