| /drivers/clk/rockchip/ |
| D | clk.h | 371 int div_shift, int div_width,
415 u8 div_shift; member
438 .div_shift = ds, \
460 .div_shift = ds, \
478 .div_shift = ds, \
496 .div_shift = ds, \
536 .div_shift = ds, \
555 .div_shift = ds, \
571 .div_shift = 16, \
588 .div_shift = 16, \
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| D | clk-ddr.c | 21 int div_shift; member
94 int div_shift, int div_width, in rockchip_clk_register_ddrclk() argument
129 ddrclk->div_shift = div_shift; in rockchip_clk_register_ddrclk()
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| D | clk.c | 41 int div_offset, u8 div_shift, u8 div_width, u8 div_flags, in rockchip_clk_register_branch() argument
94 div->shift = div_shift; in rockchip_clk_register_branch()
474 list->div_shift, list->div_width, in rockchip_clk_register_branches()
481 list->div_shift, list->div_width, in rockchip_clk_register_branches()
498 list->mux_flags, list->div_shift, in rockchip_clk_register_branches()
517 list->div_offset, list->div_shift, list->div_width, in rockchip_clk_register_branches()
527 list->div_shift in rockchip_clk_register_branches()
535 list->div_shift, list->div_flags, &ctx->lock); in rockchip_clk_register_branches()
541 list->div_shift, list->div_width, in rockchip_clk_register_branches()
550 list->mux_width, list->div_shift, in rockchip_clk_register_branches()
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| D | clk-half-divider.c | 163 u8 div_shift, u8 div_width, in rockchip_clk_register_halfdiv() argument
209 div->shift = div_shift; in rockchip_clk_register_halfdiv()
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| /drivers/clk/x86/ |
| D | clk-cgu.h | 182 u8 div_shift; member
232 .div_shift = _shift, \
272 .div_shift = _shift, \
292 .div_shift = _shift, \
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| D | clk-cgu.c | 30 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed()
199 u8 shift = list->div_shift; in lgm_clk_register_divider()
251 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed_factor()
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| /drivers/clk/imx/ |
| D | clk-pllv3.c | 52 u32 div_shift; member
114 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_recalc_rate()
142 val &= ~(pll->div_mask << pll->div_shift); in clk_pllv3_set_rate()
143 val |= (div << pll->div_shift); in clk_pllv3_set_rate()
438 pll->div_shift = 1; in imx_clk_hw_pllv3()
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| /drivers/clk/mediatek/ |
| D | clk-mtk.h | 184 unsigned char div_shift; member
195 .div_shift = _shift, \
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| D | clk-mt8167.c | 662 .div_shift = _shift, \
692 .div_shift = _shift, \
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| D | clk-mtk.c | 276 mcd->flags, base + mcd->div_reg, mcd->div_shift, in mtk_clk_register_dividers()
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| D | clk-mt8516.c | 472 .div_shift = _shift, \
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| /drivers/clk/ |
| D | clk-bm1880.c | 120 s8 div_shift; member
152 .div_shift = _div_shift, \
168 .div_shift = -1, \
803 if (clks->div_shift >= 0) { in bm1880_clk_register_composite()
812 div_hws->div.shift = clks->div_shift; in bm1880_clk_register_composite()
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| /drivers/clk/samsung/ |
| D | clk-s3c2410-dclk.c | 174 int div_shift, int cmp_shift) in s3c24xx_dclk_update_cmp() argument
183 div = ((dclk_con >> div_shift) & DCLKCON_DCLK_DIV_MASK) + 1; in s3c24xx_dclk_update_cmp()
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| /drivers/clk/at91/ |
| D | clk-sam9x60-pll.c | 253 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; in sam9x60_div_pll_prepare()
261 (div->div << core->layout->div_shift) | in sam9x60_div_pll_prepare()
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| D | pmc.h | 63 u8 div_shift; member
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| D | sam9x60.c | 55 .div_shift = 0,
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| D | sama7g5.c | 80 .div_shift = 0,
88 .div_shift = 12,
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| /drivers/mfd/ |
| D | db8500-prcmu.c | 524 u32 div_shift; member
531 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
536 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
541 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
1535 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); in dsiescclk_rate()
1900 val |= (min(div, (u32)255) << dsiescclk[n].div_shift); in set_dsiescclk_rate()
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| /drivers/clk/tegra/ |
| D | clk-tegra-periph.c | 836 u8 div_shift; member
847 .div_shift = _div_shift,\
971 data->div_shift, 8, 1, data->lock); in init_pllp()
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