| /drivers/net/ethernet/mellanox/mlx5/core/steering/ |
| D | dr_domain.c | 8 #define DR_DOMAIN_SW_STEERING_SUPPORTED(dmn, dmn_type) \ argument
9 ((dmn)->info.caps.dmn_type##_sw_owner || \
10 ((dmn)->info.caps.dmn_type##_sw_owner_v2 && \
11 (dmn)->info.caps.sw_format_ver <= MLX5_STEERING_FORMAT_CONNECTX_6DX))
13 static int dr_domain_init_cache(struct mlx5dr_domain *dmn) in dr_domain_init_cache() argument
18 dmn->cache.recalc_cs_ft = kcalloc(dmn->info.caps.num_vports, in dr_domain_init_cache()
19 sizeof(dmn->cache.recalc_cs_ft[0]), in dr_domain_init_cache()
21 if (!dmn->cache.recalc_cs_ft) in dr_domain_init_cache()
27 static void dr_domain_uninit_cache(struct mlx5dr_domain *dmn) in dr_domain_uninit_cache() argument
31 for (i = 0; i < dmn->info.caps.num_vports; i++) { in dr_domain_uninit_cache()
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| D | dr_fw.c | 8 mlx5dr_fw_create_recalc_cs_ft(struct mlx5dr_domain *dmn, u32 vport_num) in mlx5dr_fw_create_recalc_cs_ft() argument
21 ft_attr.level = dmn->info.caps.max_ft_level - 1; in mlx5dr_fw_create_recalc_cs_ft()
24 ret = mlx5dr_cmd_create_flow_table(dmn->mdev, in mlx5dr_fw_create_recalc_cs_ft()
29 mlx5dr_err(dmn, "Failed creating TTL W/A FW flow table %d\n", ret); in mlx5dr_fw_create_recalc_cs_ft()
33 ret = mlx5dr_cmd_create_empty_flow_group(dmn->mdev, in mlx5dr_fw_create_recalc_cs_ft()
37 mlx5dr_err(dmn, "Failed creating TTL W/A FW flow group %d\n", ret); in mlx5dr_fw_create_recalc_cs_ft()
46 ret = mlx5dr_cmd_alloc_modify_header(dmn->mdev, MLX5_FLOW_TABLE_TYPE_FDB, 1, in mlx5dr_fw_create_recalc_cs_ft()
50 mlx5dr_err(dmn, "Failed modify header TTL %d\n", ret); in mlx5dr_fw_create_recalc_cs_ft()
54 ret = mlx5dr_cmd_set_fte_modify_and_vport(dmn->mdev, in mlx5dr_fw_create_recalc_cs_ft()
59 mlx5dr_err(dmn, "Failed setting TTL W/A flow table entry %d\n", ret); in mlx5dr_fw_create_recalc_cs_ft()
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| D | dr_table.c | 17 mlx5dr_domain_lock(tbl->dmn); in mlx5dr_table_set_miss_action()
24 if (tbl->dmn->type == MLX5DR_DOMAIN_TYPE_NIC_RX || in mlx5dr_table_set_miss_action()
25 tbl->dmn->type == MLX5DR_DOMAIN_TYPE_FDB) { in mlx5dr_table_set_miss_action()
38 ret = mlx5dr_ste_htbl_init_and_postsend(tbl->dmn, in mlx5dr_table_set_miss_action()
43 mlx5dr_dbg(tbl->dmn, "Failed to set RX miss action, ret %d\n", ret); in mlx5dr_table_set_miss_action()
48 if (tbl->dmn->type == MLX5DR_DOMAIN_TYPE_NIC_TX || in mlx5dr_table_set_miss_action()
49 tbl->dmn->type == MLX5DR_DOMAIN_TYPE_FDB) { in mlx5dr_table_set_miss_action()
62 ret = mlx5dr_ste_htbl_init_and_postsend(tbl->dmn, in mlx5dr_table_set_miss_action()
66 mlx5dr_dbg(tbl->dmn, "Failed to set TX miss action, ret %d\n", ret); in mlx5dr_table_set_miss_action()
84 mlx5dr_domain_unlock(tbl->dmn); in mlx5dr_table_set_miss_action()
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| D | dr_action.c | 407 static void dr_actions_apply_tx(struct mlx5dr_domain *dmn, in dr_actions_apply_tx() argument
464 if (MLX5_CAP_GEN(dmn->mdev, prio_tag_required)) in dr_actions_apply_tx()
536 static void dr_actions_apply(struct mlx5dr_domain *dmn, in dr_actions_apply() argument
548 dr_actions_apply_tx(dmn, action_type_set, last_ste, attr, &added_stes); in dr_actions_apply()
592 static int dr_action_handle_cs_recalc(struct mlx5dr_domain *dmn, in dr_action_handle_cs_recalc() argument
607 mlx5dr_dbg(dmn, in dr_action_handle_cs_recalc()
617 ret = mlx5dr_domain_cache_get_recalc_cs_ft_addr(dest_action->vport.dmn, in dr_action_handle_cs_recalc()
621 mlx5dr_err(dmn, "Failed to get FW cs recalc flow table\n"); in dr_action_handle_cs_recalc()
644 struct mlx5dr_domain *dmn = matcher->tbl->dmn; in mlx5dr_actions_build_ste_arr() local
654 attr.gvmi = dmn->info.caps.gvmi; in mlx5dr_actions_build_ste_arr()
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| D | dr_send.c | 308 static int dr_handle_pending_wc(struct mlx5dr_domain *dmn, in dr_handle_pending_wc() argument
319 dmn->send_ring->signal_th * TH_NUMS_TO_DRAIN) in dr_handle_pending_wc()
353 static int dr_postsend_icm_data(struct mlx5dr_domain *dmn, in dr_postsend_icm_data() argument
356 struct mlx5dr_send_ring *send_ring = dmn->send_ring; in dr_postsend_icm_data()
362 ret = dr_handle_pending_wc(dmn, send_ring); in dr_postsend_icm_data()
366 if (send_info->write.length > dmn->info.max_inline_size) { in dr_postsend_icm_data()
368 (dmn->send_ring->signal_th - 1)) * in dr_postsend_icm_data()
387 static int dr_get_tbl_copy_details(struct mlx5dr_domain *dmn, in dr_get_tbl_copy_details() argument
396 if (htbl->chunk->byte_size > dmn->send_ring->max_post_send_size) { in dr_get_tbl_copy_details()
398 dmn->send_ring->max_post_send_size; in dr_get_tbl_copy_details()
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| D | dr_matcher.c | 122 struct mlx5dr_domain *dmn) in dr_mask_is_flex_parser_tnl_vxlan_gpe_set() argument
125 dr_matcher_supp_flex_parser_vxlan_gpe(&dmn->info.caps); in dr_mask_is_flex_parser_tnl_vxlan_gpe_set()
145 struct mlx5dr_domain *dmn) in dr_mask_is_flex_parser_tnl_geneve_set() argument
148 dr_matcher_supp_flex_parser_geneve(&dmn->info.caps); in dr_mask_is_flex_parser_tnl_geneve_set()
190 mlx5dr_dbg(matcher->tbl->dmn, in mlx5dr_matcher_select_builders()
204 struct mlx5dr_domain *dmn = matcher->tbl->dmn; in dr_matcher_set_ste_builders() local
230 ret = mlx5dr_ste_build_pre_check(dmn, matcher->match_criteria, in dr_matcher_set_ste_builders()
252 (dmn->type == MLX5DR_DOMAIN_TYPE_FDB || in dr_matcher_set_ste_builders()
253 dmn->type == MLX5DR_DOMAIN_TYPE_NIC_RX)) { in dr_matcher_set_ste_builders()
255 dmn, inner, rx); in dr_matcher_set_ste_builders()
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| D | dr_rule.c | 44 struct mlx5dr_domain *dmn = matcher->tbl->dmn; in dr_rule_create_collision_htbl() local
49 new_htbl = mlx5dr_ste_htbl_alloc(dmn->ste_icm_pool, in dr_rule_create_collision_htbl()
54 mlx5dr_dbg(dmn, "Failed allocating collision table\n"); in dr_rule_create_collision_htbl()
76 mlx5dr_dbg(matcher->tbl->dmn, "Failed creating collision entry\n"); in dr_rule_create_collision_entry()
88 mlx5dr_dbg(matcher->tbl->dmn, "Failed allocating table\n"); in dr_rule_create_collision_entry()
101 struct mlx5dr_domain *dmn) in dr_rule_handle_one_ste_in_update_list() argument
106 ret = mlx5dr_send_postsend_ste(dmn, ste_info->ste, ste_info->data, in dr_rule_handle_one_ste_in_update_list()
121 struct mlx5dr_domain *dmn, in dr_rule_send_update_list() argument
131 dmn); in dr_rule_send_update_list()
139 dmn); in dr_rule_send_update_list()
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| D | dr_types.h | 21 #define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg) argument
22 #define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg) argument
23 #define mlx5dr_dbg(dmn, arg...) mlx5_core_dbg((dmn)->mdev, ##arg) argument
190 struct mlx5dr_domain *dmn; member
283 int mlx5dr_ste_build_pre_check(struct mlx5dr_domain *dmn,
351 struct mlx5dr_domain *dmn,
686 struct mlx5dr_domain *dmn; member
736 struct mlx5dr_domain *dmn; member
747 struct mlx5dr_domain *dmn; member
756 struct mlx5dr_domain *dmn; member
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| D | dr_icm_pool.c | 50 struct mlx5dr_domain *dmn; member
100 struct mlx5_core_dev *mdev = pool->dmn->mdev; in dr_icm_pool_mr_create()
130 mlx5dr_err(pool->dmn, "Failed to allocate SW ICM memory, err (%d)\n", err); in dr_icm_pool_mr_create()
135 err = dr_icm_create_dm_mkey(mdev, pool->dmn->pdn, in dr_icm_pool_mr_create()
141 mlx5dr_err(pool->dmn, "Failed to create SW ICM MKEY, err (%d)\n", err); in dr_icm_pool_mr_create()
148 mlx5dr_err(pool->dmn, "Failed to get Aligned ICM mem (asked: %zu)\n", in dr_icm_pool_mr_create()
169 struct mlx5_core_dev *mdev = icm_mr->pool->dmn->mdev; in dr_icm_pool_mr_destroy()
465 err = mlx5dr_cmd_sync_steering(pool->dmn->mdev); in mlx5dr_icm_alloc_chunk()
468 mlx5dr_err(pool->dmn, "Sync_steering failed\n"); in mlx5dr_icm_alloc_chunk()
513 struct mlx5dr_icm_pool *mlx5dr_icm_pool_create(struct mlx5dr_domain *dmn, in mlx5dr_icm_pool_create() argument
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| D | mlx5dr.h | 48 void mlx5dr_domain_set_peer(struct mlx5dr_domain *dmn,
79 mlx5dr_action_create_dest_table_num(struct mlx5dr_domain *dmn, u32 table_num);
94 mlx5dr_action_create_mult_dest_tbl(struct mlx5dr_domain *dmn,
106 mlx5dr_action_create_packet_reformat(struct mlx5dr_domain *dmn,
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| D | dr_ste.c | 470 struct mlx5dr_domain *dmn = matcher->tbl->dmn; in mlx5dr_ste_free() local
517 mlx5dr_send_postsend_ste(dmn, cur_ste_info->ste, in mlx5dr_ste_free()
578 int mlx5dr_ste_htbl_init_and_postsend(struct mlx5dr_domain *dmn, in mlx5dr_ste_htbl_init_and_postsend() argument
586 mlx5dr_ste_set_formatted_ste(dmn->info.caps.gvmi, in mlx5dr_ste_htbl_init_and_postsend()
592 return mlx5dr_send_postsend_formatted_htbl(dmn, htbl, formatted_ste, update_hw_ste); in mlx5dr_ste_htbl_init_and_postsend()
603 struct mlx5dr_domain *dmn = matcher->tbl->dmn; in mlx5dr_ste_create_next_htbl() local
614 next_htbl = mlx5dr_ste_htbl_alloc(dmn->ste_icm_pool, in mlx5dr_ste_create_next_htbl()
619 mlx5dr_dbg(dmn, "Failed allocating table\n"); in mlx5dr_ste_create_next_htbl()
626 if (mlx5dr_ste_htbl_init_and_postsend(dmn, nic_dmn, next_htbl, in mlx5dr_ste_create_next_htbl()
628 mlx5dr_info(dmn, "Failed writing table to HW\n"); in mlx5dr_ste_create_next_htbl()
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| /drivers/powercap/ |
| D | intel_rapl_common.c | 1073 int dmn, prim; in rapl_update_domain_data() local
1076 for (dmn = 0; dmn < rp->nr_domains; dmn++) { in rapl_update_domain_data()
1078 rp->domains[dmn].name); in rapl_update_domain_data()
1081 if (!rapl_read_data_raw(&rp->domains[dmn], prim, in rapl_update_domain_data()
1083 rp->domains[dmn].rdd.primitives[prim] = val; in rapl_update_domain_data()
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