Searched refs:dramclk_khz (Results 1 – 5 of 5) sorted by relevance
219 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { in dcn2_update_clocks()220 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; in dcn2_update_clocks()222 pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000); in dcn2_update_clocks()300 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) { in dcn2_update_clocks_fpga()301 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz; in dcn2_update_clocks_fpga()413 else if (a->dramclk_khz != b->dramclk_khz) in dcn2_are_clock_states_equal()
296 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { in dcn3_update_clocks()297 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; in dcn3_update_clocks()304 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->clks.dramclk_khz / 1000); in dcn3_update_clocks()385 clk_mgr_base->clks.dramclk_khz / 1000); in dcn3_set_hard_min_memclk()434 else if (a->dramclk_khz != b->dramclk_khz) in dcn3_are_clock_states_equal()
349 int dramclk_khz; member
3031 info->memoryClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz; in get_clock_requirements_for_state()
3084 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;