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Searched refs:enable_count (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_core_irq.c73 int ret = 0, enable_count; in _dpu_core_irq_enable() local
87 enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]); in _dpu_core_irq_enable()
88 DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count); in _dpu_core_irq_enable()
89 trace_dpu_core_irq_enable_idx(irq_idx, enable_count); in _dpu_core_irq_enable()
138 int ret = 0, enable_count; in _dpu_core_irq_disable() local
150 enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]); in _dpu_core_irq_disable()
151 DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count); in _dpu_core_irq_disable()
152 trace_dpu_core_irq_disable_idx(irq_idx, enable_count); in _dpu_core_irq_disable()
296 int i, irq_count, enable_count, cb_count; in dpu_debugfs_core_irq_show() local
305 enable_count = atomic_read(&irq_obj->enable_counts[i]); in dpu_debugfs_core_irq_show()
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Ddpu_trace.h883 TP_PROTO(int irq_idx, int enable_count),
884 TP_ARGS(irq_idx, enable_count),
887 __field( int, enable_count )
891 __entry->enable_count = enable_count;
894 __entry->enable_count)
897 TP_PROTO(int irq_idx, int enable_count),
898 TP_ARGS(irq_idx, enable_count)
901 TP_PROTO(int irq_idx, int enable_count),
902 TP_ARGS(irq_idx, enable_count)
/drivers/devfreq/
Ddevfreq-event.c46 && edev->enable_count == 0) { in devfreq_event_enable_edev()
51 edev->enable_count++; in devfreq_event_enable_edev()
77 if (edev->enable_count <= 0) { in devfreq_event_disable_edev()
84 && edev->enable_count == 1) { in devfreq_event_disable_edev()
89 edev->enable_count--; in devfreq_event_disable_edev()
115 if (edev->enable_count > 0) in devfreq_event_is_enabled()
326 edev->enable_count = 0; in devfreq_event_add_edev()
360 WARN_ON(edev->enable_count); in devfreq_event_remove_edev()
459 return sprintf(buf, "%d\n", edev->enable_count); in enable_count_show()
461 static DEVICE_ATTR_RO(enable_count);
/drivers/gpu/drm/i915/
Di915_pmu.c636 BUILD_BUG_ON(ARRAY_SIZE(pmu->enable_count) != I915_PMU_MASK_BITS); in i915_pmu_enable()
637 GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count)); in i915_pmu_enable()
638 GEM_BUG_ON(pmu->enable_count[bit] == ~0); in i915_pmu_enable()
641 pmu->enable_count[bit]++; in i915_pmu_enable()
660 BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) != in i915_pmu_enable()
664 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count)); in i915_pmu_enable()
666 GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0); in i915_pmu_enable()
669 engine->pmu.enable_count[sample]++; in i915_pmu_enable()
700 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count)); in i915_pmu_disable()
702 GEM_BUG_ON(engine->pmu.enable_count[sample] == 0); in i915_pmu_disable()
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Di915_pmu.h92 unsigned int enable_count[I915_PMU_MASK_BITS]; member
/drivers/clocksource/
Dsh_tmu.c49 unsigned int enable_count; member
174 if (ch->enable_count++ > 0) in sh_tmu_enable()
197 if (WARN_ON(ch->enable_count == 0)) in sh_tmu_disable()
200 if (--ch->enable_count > 0) in sh_tmu_disable()
293 if (--ch->enable_count == 0) { in sh_tmu_clocksource_suspend()
306 if (ch->enable_count++ == 0) { in sh_tmu_clocksource_resume()
473 ch->enable_count = 0; in sh_tmu_channel_setup()
/drivers/pwm/
Dpwm-imx-tpm.c65 u32 enable_count; member
276 if (++tpm->enable_count == 1) in pwm_imx_tpm_apply_hw()
279 if (--tpm->enable_count == 0) in pwm_imx_tpm_apply_hw()
403 if (tpm->enable_count > 0) in pwm_imx_tpm_suspend()
/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_kms.h70 int enable_count; member
174 WARN_ON(mdp5_kms->enable_count <= 0); in mdp5_write()
180 WARN_ON(mdp5_kms->enable_count <= 0); in mdp5_read()
Dmdp5_kms.c301 mdp5_kms->enable_count--; in mdp5_disable()
302 WARN_ON(mdp5_kms->enable_count < 0); in mdp5_disable()
321 mdp5_kms->enable_count++; in mdp5_enable()
/drivers/net/dsa/mv88e6xxx/
Dhwtstamp.c152 chip->enable_count += 1; in mv88e6xxx_set_hwtstamp_config()
153 if (chip->enable_count == 1 && ptp_ops->global_enable) in mv88e6xxx_set_hwtstamp_config()
160 chip->enable_count -= 1; in mv88e6xxx_set_hwtstamp_config()
161 if (chip->enable_count == 0 && ptp_ops->global_disable) in mv88e6xxx_set_hwtstamp_config()
Dchip.h340 u16 enable_count; member
/drivers/regulator/
Dcore.c78 u32 enable_count; /* a number of enabled shared GPIO */ member
857 if (regulator->enable_count) in regulator_total_uA_show()
1033 if (sibling->enable_count) in drms_uA_update()
2114 regulator->enable_count = 1; in _regulator_get()
2117 regulator->enable_count = 0; in _regulator_get()
2236 WARN_ON(regulator->enable_count); in _regulator_put()
2472 if (pin->enable_count == 0) in regulator_ena_gpio_ctrl()
2475 pin->enable_count++; in regulator_ena_gpio_ctrl()
2477 if (pin->enable_count > 1) { in regulator_ena_gpio_ctrl()
2478 pin->enable_count--; in regulator_ena_gpio_ctrl()
[all …]
Dinternal.h41 unsigned int enable_count; member
/drivers/acpi/
Ddevice_pm.c761 if (wakeup->enable_count >= INT_MAX) { in __acpi_device_wakeup_enable()
765 if (wakeup->enable_count > 0) in __acpi_device_wakeup_enable()
783 wakeup->enable_count++; in __acpi_device_wakeup_enable()
822 if (!wakeup->enable_count) in acpi_device_wakeup_disable()
828 wakeup->enable_count--; in acpi_device_wakeup_disable()
/drivers/clk/
Dclk.c77 unsigned int enable_count; member
236 return core->enable_count; in clk_core_is_enabled()
483 return !clk ? 0 : clk->core->enable_count; in __clk_get_enable_count()
855 WARN(core->enable_count > 0, "Unpreparing enabled %s\n", core->name); in clk_core_unprepare()
982 if (WARN(core->enable_count == 0, "%s already disabled\n", core->name)) in clk_core_disable()
985 if (WARN(core->enable_count == 1 && core->flags & CLK_IS_CRITICAL, in clk_core_disable()
989 if (--core->enable_count > 0) in clk_core_disable()
1045 if (core->enable_count == 0) { in clk_core_enable()
1064 core->enable_count++; in clk_core_enable()
1094 if (core->enable_count) in clk_gate_restore_context()
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/drivers/gpu/drm/i915/gt/
Dintel_engine_types.h393 unsigned int enable_count[I915_ENGINE_SAMPLE_COUNT]; member