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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Atlantic Network Driver
3  *
4  * Copyright (C) 2014-2019 aQuantia Corporation
5  * Copyright (C) 2019-2020 Marvell International Ltd.
6  */
7 
8 /* File hw_atl_utils.h: Declaration of common functions for Atlantic hardware
9  * abstraction layer.
10  */
11 
12 #ifndef HW_ATL_UTILS_H
13 #define HW_ATL_UTILS_H
14 
15 #define HW_ATL_FLUSH() { (void)aq_hw_read_reg(self, 0x10); }
16 
17 /* Hardware tx descriptor */
18 struct __packed hw_atl_txd_s {
19 	u64 buf_addr;
20 	u32 ctl;
21 	u32 ctl2; /* 63..46 - payload length, 45 - ctx enable, 44 - ctx index */
22 };
23 
24 /* Hardware tx context descriptor */
25 struct __packed hw_atl_txc_s {
26 	u32 rsvd;
27 	u32 len;
28 	u32 ctl;
29 	u32 len2;
30 };
31 
32 /* Hardware rx descriptor */
33 struct __packed hw_atl_rxd_s {
34 	u64 buf_addr;
35 	u64 hdr_addr;
36 };
37 
38 /* Hardware rx descriptor writeback */
39 struct __packed hw_atl_rxd_wb_s {
40 	u32 type;
41 	u32 rss_hash;
42 	u16 status;
43 	u16 pkt_len;
44 	u16 next_desc_ptr;
45 	__le16 vlan;
46 };
47 
48 /* Hardware rx HW TIMESTAMP writeback */
49 struct __packed hw_atl_rxd_hwts_wb_s {
50 	u32 sec_hw;
51 	u32 ns;
52 	u32 sec_lw0;
53 	u32 sec_lw1;
54 };
55 
56 struct __packed hw_atl_stats_s {
57 	u32 uprc;
58 	u32 mprc;
59 	u32 bprc;
60 	u32 erpt;
61 	u32 uptc;
62 	u32 mptc;
63 	u32 bptc;
64 	u32 erpr;
65 	u32 mbtc;
66 	u32 bbtc;
67 	u32 mbrc;
68 	u32 bbrc;
69 	u32 ubrc;
70 	u32 ubtc;
71 	u32 dpc;
72 };
73 
74 struct __packed drv_msg_enable_wakeup {
75 	union {
76 		u32 pattern_mask;
77 
78 		struct {
79 			u32 reason_arp_v4_pkt : 1;
80 			u32 reason_ipv4_ping_pkt : 1;
81 			u32 reason_ipv6_ns_pkt : 1;
82 			u32 reason_ipv6_ping_pkt : 1;
83 			u32 reason_link_up : 1;
84 			u32 reason_link_down : 1;
85 			u32 reason_maximum : 1;
86 		};
87 	};
88 
89 	union {
90 		u32 offload_mask;
91 	};
92 };
93 
94 struct __packed magic_packet_pattern_s {
95 	u8 mac_addr[ETH_ALEN];
96 };
97 
98 struct __packed drv_msg_wol_add {
99 	u32 priority;
100 	u32 packet_type;
101 	u32 pattern_id;
102 	u32 next_pattern_offset;
103 
104 	struct magic_packet_pattern_s magic_packet_pattern;
105 };
106 
107 struct __packed drv_msg_wol_remove {
108 	u32 id;
109 };
110 
111 struct __packed hw_atl_utils_mbox_header {
112 	u32 version;
113 	u32 transaction_id;
114 	u32 error;
115 };
116 
117 struct __packed hw_atl_ptp_offset {
118 	u16 ingress_100;
119 	u16 egress_100;
120 	u16 ingress_1000;
121 	u16 egress_1000;
122 	u16 ingress_2500;
123 	u16 egress_2500;
124 	u16 ingress_5000;
125 	u16 egress_5000;
126 	u16 ingress_10000;
127 	u16 egress_10000;
128 };
129 
130 struct __packed hw_atl_cable_diag {
131 	u8 fault;
132 	u8 distance;
133 	u8 far_distance;
134 	u8 reserved;
135 };
136 
137 enum gpio_pin_function {
138 	GPIO_PIN_FUNCTION_NC,
139 	GPIO_PIN_FUNCTION_VAUX_ENABLE,
140 	GPIO_PIN_FUNCTION_EFUSE_BURN_ENABLE,
141 	GPIO_PIN_FUNCTION_SFP_PLUS_DETECT,
142 	GPIO_PIN_FUNCTION_TX_DISABLE,
143 	GPIO_PIN_FUNCTION_RATE_SEL_0,
144 	GPIO_PIN_FUNCTION_RATE_SEL_1,
145 	GPIO_PIN_FUNCTION_TX_FAULT,
146 	GPIO_PIN_FUNCTION_PTP0,
147 	GPIO_PIN_FUNCTION_PTP1,
148 	GPIO_PIN_FUNCTION_PTP2,
149 	GPIO_PIN_FUNCTION_SIZE
150 };
151 
152 struct __packed hw_atl_info {
153 	u8 reserved[6];
154 	u16 phy_fault_code;
155 	u16 phy_temperature;
156 	u8 cable_len;
157 	u8 reserved1;
158 	struct hw_atl_cable_diag cable_diag_data[4];
159 	struct hw_atl_ptp_offset ptp_offset;
160 	u8 reserved2[12];
161 	u32 caps_lo;
162 	u32 caps_hi;
163 	u32 reserved_datapath;
164 	u32 reserved3[7];
165 	u32 reserved_simpleresp[3];
166 	u32 reserved_linkstat[7];
167 	u32 reserved_wakes_count;
168 	u32 reserved_eee_stat[12];
169 	u32 tx_stuck_cnt;
170 	u32 setting_address;
171 	u32 setting_length;
172 	u32 caps_ex;
173 	enum gpio_pin_function gpio_pin[3];
174 	u32 pcie_aer_dump[18];
175 	u16 snr_margin[4];
176 };
177 
178 struct __packed hw_atl_utils_mbox {
179 	struct hw_atl_utils_mbox_header header;
180 	struct hw_atl_stats_s stats;
181 	struct hw_atl_info info;
182 };
183 
184 struct __packed offload_ip_info {
185 	u8 v4_local_addr_count;
186 	u8 v4_addr_count;
187 	u8 v6_local_addr_count;
188 	u8 v6_addr_count;
189 	u32 v4_addr;
190 	u32 v4_prefix;
191 	u32 v6_addr;
192 	u32 v6_prefix;
193 };
194 
195 struct __packed offload_port_info {
196 	u16 udp_port_count;
197 	u16 tcp_port_count;
198 	u32 udp_port;
199 	u32 tcp_port;
200 };
201 
202 struct __packed offload_ka_info {
203 	u16 v4_ka_count;
204 	u16 v6_ka_count;
205 	u32 retry_count;
206 	u32 retry_interval;
207 	u32 v4_ka;
208 	u32 v6_ka;
209 };
210 
211 struct __packed offload_rr_info {
212 	u32 rr_count;
213 	u32 rr_buf_len;
214 	u32 rr_id_x;
215 	u32 rr_buf;
216 };
217 
218 struct __packed offload_info {
219 	u32 version;
220 	u32 len;
221 	u8 mac_addr[ETH_ALEN];
222 
223 	u8 reserved[2];
224 
225 	struct offload_ip_info ips;
226 	struct offload_port_info ports;
227 	struct offload_ka_info kas;
228 	struct offload_rr_info rrs;
229 	u8 buf[];
230 };
231 
232 struct __packed hw_atl_utils_fw_rpc {
233 	u32 msg_id;
234 
235 	union {
236 		/* fw1x structures */
237 		struct drv_msg_wol_add msg_wol_add;
238 		struct drv_msg_wol_remove msg_wol_remove;
239 		struct drv_msg_enable_wakeup msg_enable_wakeup;
240 		/* fw2x structures */
241 		struct offload_info fw2x_offloads;
242 	};
243 };
244 
245 /* Mailbox FW Request interface */
246 struct __packed hw_fw_request_ptp_gpio_ctrl {
247 	u32 index;
248 	u32 period;
249 	u64 start;
250 };
251 
252 struct __packed hw_fw_request_ptp_adj_freq {
253 	u32 ns_mac;
254 	u32 fns_mac;
255 	u32 ns_phy;
256 	u32 fns_phy;
257 	u32 mac_ns_adj;
258 	u32 mac_fns_adj;
259 };
260 
261 struct __packed hw_fw_request_ptp_adj_clock {
262 	u32 ns;
263 	u32 sec;
264 	int sign;
265 };
266 
267 #define HW_AQ_FW_REQUEST_PTP_GPIO_CTRL	         0x11
268 #define HW_AQ_FW_REQUEST_PTP_ADJ_FREQ	         0x12
269 #define HW_AQ_FW_REQUEST_PTP_ADJ_CLOCK	         0x13
270 
271 struct __packed hw_fw_request_iface {
272 	u32 msg_id;
273 	union {
274 		/* PTP FW Request */
275 		struct hw_fw_request_ptp_gpio_ctrl ptp_gpio_ctrl;
276 		struct hw_fw_request_ptp_adj_freq ptp_adj_freq;
277 		struct hw_fw_request_ptp_adj_clock ptp_adj_clock;
278 	};
279 };
280 
281 struct __packed hw_atl_utils_settings {
282 	u32 mtu;
283 	u32 downshift_retry_count;
284 	u32 link_pause_frame_quanta_100m;
285 	u32 link_pause_frame_threshold_100m;
286 	u32 link_pause_frame_quanta_1g;
287 	u32 link_pause_frame_threshold_1g;
288 	u32 link_pause_frame_quanta_2p5g;
289 	u32 link_pause_frame_threshold_2p5g;
290 	u32 link_pause_frame_quanta_5g;
291 	u32 link_pause_frame_threshold_5g;
292 	u32 link_pause_frame_quanta_10g;
293 	u32 link_pause_frame_threshold_10g;
294 	u32 pfc_quanta_class_0;
295 	u32 pfc_threshold_class_0;
296 	u32 pfc_quanta_class_1;
297 	u32 pfc_threshold_class_1;
298 	u32 pfc_quanta_class_2;
299 	u32 pfc_threshold_class_2;
300 	u32 pfc_quanta_class_3;
301 	u32 pfc_threshold_class_3;
302 	u32 pfc_quanta_class_4;
303 	u32 pfc_threshold_class_4;
304 	u32 pfc_quanta_class_5;
305 	u32 pfc_threshold_class_5;
306 	u32 pfc_quanta_class_6;
307 	u32 pfc_threshold_class_6;
308 	u32 pfc_quanta_class_7;
309 	u32 pfc_threshold_class_7;
310 	u32 eee_link_down_timeout;
311 	u32 eee_link_up_timeout;
312 	u32 eee_max_link_drops;
313 	u32 eee_rates_mask;
314 	u32 wake_timer;
315 	u32 thermal_shutdown_off_temp;
316 	u32 thermal_shutdown_warning_temp;
317 	u32 thermal_shutdown_cold_temp;
318 	u32 msm_options;
319 	u32 dac_cable_serdes_modes;
320 	u32 media_detect;
321 };
322 
323 enum macsec_msg_type {
324 	macsec_cfg_msg = 0,
325 	macsec_add_rx_sc_msg,
326 	macsec_add_tx_sc_msg,
327 	macsec_add_rx_sa_msg,
328 	macsec_add_tx_sa_msg,
329 	macsec_get_stats_msg,
330 };
331 
332 struct __packed macsec_cfg_request {
333 	u32 enabled;
334 	u32 egress_threshold;
335 	u32 ingress_threshold;
336 	u32 interrupts_enabled;
337 };
338 
339 struct __packed macsec_msg_fw_request {
340 	u32 msg_id; /* not used */
341 	u32 msg_type;
342 	struct macsec_cfg_request cfg;
343 };
344 
345 struct __packed macsec_msg_fw_response {
346 	u32 result;
347 };
348 
349 enum hw_atl_rx_action_with_traffic {
350 	HW_ATL_RX_DISCARD,
351 	HW_ATL_RX_HOST,
352 	HW_ATL_RX_MNGMNT,
353 	HW_ATL_RX_HOST_AND_MNGMNT,
354 	HW_ATL_RX_WOL
355 };
356 
357 struct aq_rx_filter_vlan {
358 	u8 enable;
359 	u8 location;
360 	u16 vlan_id;
361 	u8 queue;
362 };
363 
364 #define HW_ATL_VLAN_MAX_FILTERS         16U
365 
366 struct aq_rx_filter_l2 {
367 	s8 queue;
368 	u8 location;
369 	u8 user_priority_en;
370 	u8 user_priority;
371 	u16 ethertype;
372 };
373 
374 struct aq_rx_filter_l3l4 {
375 	u32 cmd;
376 	u8 location;
377 	u32 ip_dst[4];
378 	u32 ip_src[4];
379 	u16 p_dst;
380 	u16 p_src;
381 	u8 is_ipv6;
382 };
383 
384 enum hw_atl_rx_protocol_value_l3l4 {
385 	HW_ATL_RX_TCP,
386 	HW_ATL_RX_UDP,
387 	HW_ATL_RX_SCTP,
388 	HW_ATL_RX_ICMP
389 };
390 
391 enum hw_atl_rx_ctrl_registers_l3l4 {
392 	HW_ATL_RX_ENABLE_MNGMNT_QUEUE_L3L4 = BIT(22),
393 	HW_ATL_RX_ENABLE_QUEUE_L3L4        = BIT(23),
394 	HW_ATL_RX_ENABLE_ARP_FLTR_L3       = BIT(24),
395 	HW_ATL_RX_ENABLE_CMP_PROT_L4       = BIT(25),
396 	HW_ATL_RX_ENABLE_CMP_DEST_PORT_L4  = BIT(26),
397 	HW_ATL_RX_ENABLE_CMP_SRC_PORT_L4   = BIT(27),
398 	HW_ATL_RX_ENABLE_CMP_DEST_ADDR_L3  = BIT(28),
399 	HW_ATL_RX_ENABLE_CMP_SRC_ADDR_L3   = BIT(29),
400 	HW_ATL_RX_ENABLE_L3_IPV6           = BIT(30),
401 	HW_ATL_RX_ENABLE_FLTR_L3L4         = BIT(31)
402 };
403 
404 #define HW_ATL_RX_QUEUE_FL3L4_SHIFT       8U
405 #define HW_ATL_RX_ACTION_FL3F4_SHIFT      16U
406 
407 #define HW_ATL_RX_CNT_REG_ADDR_IPV6       4U
408 
409 #define HW_ATL_GET_REG_LOCATION_FL3L4(location) \
410 	((location) - AQ_RX_FIRST_LOC_FL3L4)
411 
412 enum hal_atl_utils_fw_state_e {
413 	MPI_DEINIT = 0,
414 	MPI_RESET = 1,
415 	MPI_INIT = 2,
416 	MPI_POWER = 4,
417 };
418 
419 #define HAL_ATLANTIC_RATE_10G        BIT(0)
420 #define HAL_ATLANTIC_RATE_5G         BIT(1)
421 #define HAL_ATLANTIC_RATE_5GSR       BIT(2)
422 #define HAL_ATLANTIC_RATE_2G5        BIT(3)
423 #define HAL_ATLANTIC_RATE_1G         BIT(4)
424 #define HAL_ATLANTIC_RATE_100M       BIT(5)
425 #define HAL_ATLANTIC_RATE_INVALID    BIT(6)
426 
427 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_ADD       0x4U
428 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_PRIOR     0x10000000U
429 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_PATTERN   0x1U
430 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_MAG_PKT   0x2U
431 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_DEL       0x5U
432 #define HAL_ATLANTIC_UTILS_FW_MSG_ENABLE_WAKEUP 0x6U
433 
434 enum hw_atl_fw2x_rate {
435 	FW2X_RATE_100M    = 0x20,
436 	FW2X_RATE_1G      = 0x100,
437 	FW2X_RATE_2G5     = 0x200,
438 	FW2X_RATE_5G      = 0x400,
439 	FW2X_RATE_10G     = 0x800,
440 };
441 
442 /* 0x370
443  * Link capabilities resolution register
444  */
445 enum hw_atl_fw2x_caps_lo {
446 	CAPS_LO_10BASET_HD        = 0,
447 	CAPS_LO_10BASET_FD,
448 	CAPS_LO_100BASETX_HD,
449 	CAPS_LO_100BASET4_HD,
450 	CAPS_LO_100BASET2_HD,
451 	CAPS_LO_100BASETX_FD      = 5,
452 	CAPS_LO_100BASET2_FD,
453 	CAPS_LO_1000BASET_HD,
454 	CAPS_LO_1000BASET_FD,
455 	CAPS_LO_2P5GBASET_FD,
456 	CAPS_LO_5GBASET_FD        = 10,
457 	CAPS_LO_10GBASET_FD,
458 	CAPS_LO_AUTONEG,
459 	CAPS_LO_SMBUS_READ,
460 	CAPS_LO_SMBUS_WRITE,
461 	CAPS_LO_MACSEC            = 15,
462 	CAPS_LO_RESERVED1,
463 	CAPS_LO_WAKE_ON_LINK_FORCED,
464 	CAPS_LO_HIGH_TEMP_WARNING = 29,
465 	CAPS_LO_DRIVER_SCRATCHPAD = 30,
466 	CAPS_LO_GLOBAL_FAULT      = 31
467 };
468 
469 /* 0x374
470  * Status register
471  */
472 enum hw_atl_fw2x_caps_hi {
473 	CAPS_HI_TPO2EN            = 0,
474 	CAPS_HI_10BASET_EEE,
475 	CAPS_HI_RESERVED2,
476 	CAPS_HI_PAUSE,
477 	CAPS_HI_ASYMMETRIC_PAUSE,
478 	CAPS_HI_100BASETX_EEE     = 5,
479 	CAPS_HI_PHY_BUF_SEND,
480 	CAPS_HI_PHY_BUF_RECV,
481 	CAPS_HI_1000BASET_FD_EEE,
482 	CAPS_HI_2P5GBASET_FD_EEE,
483 	CAPS_HI_5GBASET_FD_EEE    = 10,
484 	CAPS_HI_10GBASET_FD_EEE,
485 	CAPS_HI_FW_REQUEST,
486 	CAPS_HI_PHY_LOG,
487 	CAPS_HI_EEE_AUTO_DISABLE_SETTINGS,
488 	CAPS_HI_PFC               = 15,
489 	CAPS_HI_WAKE_ON_LINK,
490 	CAPS_HI_CABLE_DIAG,
491 	CAPS_HI_TEMPERATURE,
492 	CAPS_HI_DOWNSHIFT,
493 	CAPS_HI_PTP_AVB_EN_FW2X   = 20,
494 	CAPS_HI_THERMAL_SHUTDOWN,
495 	CAPS_HI_LINK_DROP,
496 	CAPS_HI_SLEEP_PROXY,
497 	CAPS_HI_WOL,
498 	CAPS_HI_MAC_STOP          = 25,
499 	CAPS_HI_EXT_LOOPBACK,
500 	CAPS_HI_INT_LOOPBACK,
501 	CAPS_HI_EFUSE_AGENT,
502 	CAPS_HI_WOL_TIMER,
503 	CAPS_HI_STATISTICS        = 30,
504 	CAPS_HI_TRANSACTION_ID,
505 };
506 
507 /* 0x36C
508  * Control register
509  */
510 enum hw_atl_fw2x_ctrl {
511 	CTRL_RESERVED1            = 0,
512 	CTRL_RESERVED2,
513 	CTRL_RESERVED3,
514 	CTRL_PAUSE,
515 	CTRL_ASYMMETRIC_PAUSE,
516 	CTRL_RESERVED4            = 5,
517 	CTRL_RESERVED5,
518 	CTRL_RESERVED6,
519 	CTRL_1GBASET_FD_EEE,
520 	CTRL_2P5GBASET_FD_EEE,
521 	CTRL_5GBASET_FD_EEE       = 10,
522 	CTRL_10GBASET_FD_EEE,
523 	CTRL_THERMAL_SHUTDOWN,
524 	CTRL_PHY_LOGS,
525 	CTRL_EEE_AUTO_DISABLE,
526 	CTRL_PFC                  = 15,
527 	CTRL_WAKE_ON_LINK,
528 	CTRL_CABLE_DIAG,
529 	CTRL_TEMPERATURE,
530 	CTRL_DOWNSHIFT,
531 	CTRL_PTP_AVB              = 20,
532 	CTRL_RESERVED7,
533 	CTRL_LINK_DROP,
534 	CTRL_SLEEP_PROXY,
535 	CTRL_WOL,
536 	CTRL_MAC_STOP             = 25,
537 	CTRL_EXT_LOOPBACK,
538 	CTRL_INT_LOOPBACK,
539 	CTRL_RESERVED8,
540 	CTRL_WOL_TIMER,
541 	CTRL_STATISTICS           = 30,
542 	CTRL_FORCE_RECONNECT,
543 };
544 
545 enum hw_atl_caps_ex {
546 	CAPS_EX_LED_CONTROL       =  0,
547 	CAPS_EX_LED0_MODE_LO,
548 	CAPS_EX_LED0_MODE_HI,
549 	CAPS_EX_LED1_MODE_LO,
550 	CAPS_EX_LED1_MODE_HI,
551 	CAPS_EX_LED2_MODE_LO      =  5,
552 	CAPS_EX_LED2_MODE_HI,
553 	CAPS_EX_RESERVED07,
554 	CAPS_EX_RESERVED08,
555 	CAPS_EX_RESERVED09,
556 	CAPS_EX_RESERVED10        = 10,
557 	CAPS_EX_RESERVED11,
558 	CAPS_EX_RESERVED12,
559 	CAPS_EX_RESERVED13,
560 	CAPS_EX_RESERVED14,
561 	CAPS_EX_RESERVED15        = 15,
562 	CAPS_EX_PHY_PTP_EN,
563 	CAPS_EX_MAC_PTP_EN,
564 	CAPS_EX_EXT_CLK_EN,
565 	CAPS_EX_SCHED_DMA_EN,
566 	CAPS_EX_PTP_GPIO_EN       = 20,
567 	CAPS_EX_UPDATE_SETTINGS,
568 	CAPS_EX_PHY_CTRL_TS_PIN,
569 	CAPS_EX_SNR_OPERATING_MARGIN,
570 	CAPS_EX_RESERVED24,
571 	CAPS_EX_RESERVED25        = 25,
572 	CAPS_EX_RESERVED26,
573 	CAPS_EX_RESERVED27,
574 	CAPS_EX_RESERVED28,
575 	CAPS_EX_RESERVED29,
576 	CAPS_EX_RESERVED30        = 30,
577 	CAPS_EX_RESERVED31
578 };
579 
580 struct aq_hw_s;
581 struct aq_fw_ops;
582 struct aq_hw_caps_s;
583 struct aq_hw_link_status_s;
584 
585 int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops);
586 
587 int hw_atl_utils_soft_reset(struct aq_hw_s *self);
588 
589 void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p);
590 
591 int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self,
592 			       struct hw_atl_utils_mbox_header *pmbox);
593 
594 void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
595 				 struct hw_atl_utils_mbox *pmbox);
596 
597 void hw_atl_utils_mpi_set(struct aq_hw_s *self,
598 			  enum hal_atl_utils_fw_state_e state,
599 			  u32 speed);
600 
601 int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self);
602 
603 int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self,
604 				   u8 *mac);
605 
606 unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps);
607 
608 int hw_atl_utils_hw_get_regs(struct aq_hw_s *self,
609 			     const struct aq_hw_caps_s *aq_hw_caps,
610 			     u32 *regs_buff);
611 
612 int hw_atl_utils_hw_set_power(struct aq_hw_s *self,
613 			      unsigned int power_state);
614 
615 int hw_atl_utils_hw_deinit(struct aq_hw_s *self);
616 
617 u32 hw_atl_utils_get_fw_version(struct aq_hw_s *self);
618 
619 int hw_atl_utils_update_stats(struct aq_hw_s *self);
620 
621 struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self);
622 
623 int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
624 				  u32 *p, u32 cnt);
625 
626 int hw_atl_write_fwcfg_dwords(struct aq_hw_s *self, u32 *p, u32 cnt);
627 
628 int hw_atl_write_fwsettings_dwords(struct aq_hw_s *self, u32 offset, u32 *p,
629 				   u32 cnt);
630 
631 int hw_atl_utils_fw_set_wol(struct aq_hw_s *self, bool wol_enabled, u8 *mac);
632 
633 int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size);
634 
635 int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self,
636 			     struct hw_atl_utils_fw_rpc **rpc);
637 
638 bool hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual);
639 
640 extern const struct aq_fw_ops aq_fw_1x_ops;
641 extern const struct aq_fw_ops aq_fw_2x_ops;
642 
643 #endif /* HW_ATL_UTILS_H */
644