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Searched refs:grph (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hubbub.c343 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub3_get_dcc_compression_cap()
344 output->grph.rgb.max_compressed_blk_size = 256; in hubbub3_get_dcc_compression_cap()
345 output->grph.rgb.independent_64b_blks = false; in hubbub3_get_dcc_compression_cap()
346 output->grph.rgb.dcc_controls.dcc_256_256_unconstrained = 1; in hubbub3_get_dcc_compression_cap()
347 output->grph.rgb.dcc_controls.dcc_256_128_128 = 1; in hubbub3_get_dcc_compression_cap()
350 output->grph.rgb.max_uncompressed_blk_size = 128; in hubbub3_get_dcc_compression_cap()
351 output->grph.rgb.max_compressed_blk_size = 128; in hubbub3_get_dcc_compression_cap()
352 output->grph.rgb.independent_64b_blks = false; in hubbub3_get_dcc_compression_cap()
353 output->grph.rgb.dcc_controls.dcc_128_128_uncontrained = 1; in hubbub3_get_dcc_compression_cap()
354 output->grph.rgb.dcc_controls.dcc_256_128_128 = 1; in hubbub3_get_dcc_compression_cap()
[all …]
Ddcn30_hubp.c112 if (address->grph.addr.quad_part == 0) in hubp3_program_surface_flip_and_addr()
119 if (address->grph.meta_addr.quad_part != 0) { in hubp3_program_surface_flip_and_addr()
122 address->grph.meta_addr.high_part); in hubp3_program_surface_flip_and_addr()
126 address->grph.meta_addr.low_part); in hubp3_program_surface_flip_and_addr()
131 address->grph.addr.high_part); in hubp3_program_surface_flip_and_addr()
135 address->grph.addr.low_part); in hubp3_program_surface_flip_and_addr()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hubbub.c286 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub2_get_dcc_compression_cap()
287 output->grph.rgb.max_compressed_blk_size = 256; in hubbub2_get_dcc_compression_cap()
288 output->grph.rgb.independent_64b_blks = false; in hubbub2_get_dcc_compression_cap()
291 output->grph.rgb.max_uncompressed_blk_size = 128; in hubbub2_get_dcc_compression_cap()
292 output->grph.rgb.max_compressed_blk_size = 128; in hubbub2_get_dcc_compression_cap()
293 output->grph.rgb.independent_64b_blks = false; in hubbub2_get_dcc_compression_cap()
296 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub2_get_dcc_compression_cap()
297 output->grph.rgb.max_compressed_blk_size = 64; in hubbub2_get_dcc_compression_cap()
298 output->grph.rgb.independent_64b_blks = true; in hubbub2_get_dcc_compression_cap()
Ddcn20_hubp.c741 if (address->grph.addr.quad_part == 0) in hubp2_program_surface_flip_and_addr()
748 if (address->grph.meta_addr.quad_part != 0) { in hubp2_program_surface_flip_and_addr()
751 address->grph.meta_addr.high_part); in hubp2_program_surface_flip_and_addr()
755 address->grph.meta_addr.low_part); in hubp2_program_surface_flip_and_addr()
760 address->grph.addr.high_part); in hubp2_program_surface_flip_and_addr()
764 address->grph.addr.low_part); in hubp2_program_surface_flip_and_addr()
921 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); in hubp2_is_flip_pending()
924 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); in hubp2_is_flip_pending()
929 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) in hubp2_is_flip_pending()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hubbub.c908 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub1_get_dcc_compression_cap()
909 output->grph.rgb.max_compressed_blk_size = 256; in hubbub1_get_dcc_compression_cap()
910 output->grph.rgb.independent_64b_blks = false; in hubbub1_get_dcc_compression_cap()
913 output->grph.rgb.max_uncompressed_blk_size = 128; in hubbub1_get_dcc_compression_cap()
914 output->grph.rgb.max_compressed_blk_size = 128; in hubbub1_get_dcc_compression_cap()
915 output->grph.rgb.independent_64b_blks = false; in hubbub1_get_dcc_compression_cap()
918 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub1_get_dcc_compression_cap()
919 output->grph.rgb.max_compressed_blk_size = 64; in hubbub1_get_dcc_compression_cap()
920 output->grph.rgb.independent_64b_blks = true; in hubbub1_get_dcc_compression_cap()
Ddcn10_hubp.c388 if (address->grph.addr.quad_part == 0) in hubp1_program_surface_flip_and_addr()
395 if (address->grph.meta_addr.quad_part != 0) { in hubp1_program_surface_flip_and_addr()
398 address->grph.meta_addr.high_part); in hubp1_program_surface_flip_and_addr()
402 address->grph.meta_addr.low_part); in hubp1_program_surface_flip_and_addr()
407 address->grph.addr.high_part); in hubp1_program_surface_flip_and_addr()
411 address->grph.addr.low_part); in hubp1_program_surface_flip_and_addr()
744 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); in hubp1_is_flip_pending()
747 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); in hubp1_is_flip_pending()
752 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) in hubp1_is_flip_pending()
/drivers/gpu/drm/amd/display/dc/core/
Ddc_debug.c83 plane_state->address.grph.addr.quad_part, in pre_surface_trace()
84 plane_state->address.grph.meta_addr.quad_part, in pre_surface_trace()
195 update->flip_addr->address.grph.addr.quad_part, in update_surface_trace()
196 update->flip_addr->address.grph.meta_addr.quad_part, in update_surface_trace()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hubp.c711 if (address->grph.addr.quad_part == 0) { in hubp21_program_surface_flip_and_addr()
716 if (address->grph.meta_addr.quad_part != 0) { in hubp21_program_surface_flip_and_addr()
718 address->grph.meta_addr.low_part; in hubp21_program_surface_flip_and_addr()
720 address->grph.meta_addr.high_part; in hubp21_program_surface_flip_and_addr()
724 address->grph.addr.low_part; in hubp21_program_surface_flip_and_addr()
726 address->grph.addr.high_part; in hubp21_program_surface_flip_and_addr()
/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_hw_sequencer.c351 pipe_ctx->plane_state->address.grph.addr.high_part, in dce60_program_front_end_for_pipe()
352 pipe_ctx->plane_state->address.grph.addr.low_part, in dce60_program_front_end_for_pipe()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_mem_input.c851 if (address->grph.addr.quad_part == 0) in dce_mi_program_surface_flip_and_addr()
853 program_pri_addr(dce_mi, address->grph.addr); in dce_mi_program_surface_flip_and_addr()
/drivers/gpu/drm/amd/display/dc/
Ddc_hw_types.h78 } grph; member
Ddc.h207 } grph; member
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_mem_input_v.c137 addr->grph.addr); in program_addr()
Ddce110_hw_sequencer.c2622 pipe_ctx->plane_state->address.grph.addr.high_part, in dce110_program_front_end_for_pipe()
2623 pipe_ctx->plane_state->address.grph.addr.low_part, in dce110_program_front_end_for_pipe()
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm.c3898 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0) in fill_plane_dcc_attributes()
3907 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); in fill_plane_dcc_attributes()
3908 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); in fill_plane_dcc_attributes()
3945 address->grph.addr.low_part = lower_32_bits(afb->address); in fill_plane_buffer_attributes()
3946 address->grph.addr.high_part = upper_32_bits(afb->address); in fill_plane_buffer_attributes()
7341 bundle->flip_addrs[planes_count].address.grph.addr.high_part, in amdgpu_dm_commit_planes()
7342 bundle->flip_addrs[planes_count].address.grph.addr.low_part); in amdgpu_dm_commit_planes()