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Searched refs:hubps (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer_debug.c134 struct hubp *hubp = pool->hubps[i]; in dcn10_get_hubp_states()
204 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state); in dcn10_get_rq_states()
212 …pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expan… in dcn10_get_rq_states()
249 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state); in dcn10_get_dlg_states()
260 …pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_… in dcn10_get_dlg_states()
303 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state); in dcn10_get_ttu_states()
311 …pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_v… in dcn10_get_ttu_states()
510 struct hubp *hubp = pool->hubps[i]; in dcn10_clear_hubp_underflow()
Ddcn10_resource.c996 if (pool->base.hubps[i] != NULL) { in dcn10_resource_destruct()
997 kfree(TO_DCN10_HUBP(pool->base.hubps[i])); in dcn10_resource_destruct()
998 pool->base.hubps[i] = NULL; in dcn10_resource_destruct()
1172 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1561 pool->base.hubps[j] = dcn10_hubp_create(ctx, i); in dcn10_resource_construct()
1562 if (pool->base.hubps[j] == NULL) { in dcn10_resource_construct()
Ddcn10_hw_sequencer.c165 struct hubp *hubp = pool->hubps[i]; in dcn10_log_hubp_states()
197 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state); in dcn10_log_hubp_states()
202 …pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expan… in dcn10_log_hubp_states()
222 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state); in dcn10_log_hubp_states()
229 …pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_… in dcn10_log_hubp_states()
254 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state); in dcn10_log_hubp_states()
259 …pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_v… in dcn10_log_hubp_states()
666 struct hubp *hubp = dc->res_pool->hubps[0]; in undo_DEGVIDCN10_253_wa()
686 struct hubp *hubp = dc->res_pool->hubps[0]; in apply_DEGVIDCN10_253_wa()
696 if (!dc->res_pool->hubps[i]->power_gated) in apply_DEGVIDCN10_253_wa()
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/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c941 if (pool->base.hubps[i] != NULL) { in dcn21_resource_destruct()
942 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); in dcn21_resource_destruct()
943 pool->base.hubps[i] = NULL; in dcn21_resource_destruct()
1991 pool->base.hubps[j] = dcn21_hubp_create(ctx, i); in dcn21_resource_construct()
1992 if (pool->base.hubps[j] == NULL) { in dcn21_resource_construct()
/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h183 struct hubp *hubps[MAX_PIPES]; member
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_resource.c1240 if (pool->base.hubps[i] != NULL) { in dcn30_resource_destruct()
1241 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); in dcn30_resource_destruct()
1242 pool->base.hubps[i] = NULL; in dcn30_resource_destruct()
1864 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
2746 pool->base.hubps[i] = dcn30_hubp_create(ctx, i); in dcn30_resource_construct()
2747 if (pool->base.hubps[i] == NULL) { in dcn30_resource_construct()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c1490 if (pool->base.hubps[i] != NULL) { in dcn20_resource_destruct()
1491 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); in dcn20_resource_destruct()
1492 pool->base.hubps[i] = NULL; in dcn20_resource_destruct()
1877 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1952 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
3281 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
4001 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
4002 if (pool->base.hubps[i] == NULL) {
Ddcn20_hwseq.c2483 struct hubp *hubp = dc->res_pool->hubps[i]; in dcn20_fpga_init_hw()
/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c1403 split_pipe->plane_res.hubp = pool->hubps[i]; in acquire_first_split_pipe()
1780 pipe_ctx->plane_res.hubp = pool->hubps[i]; in acquire_first_free_pipe()
2036 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst]; in acquire_resource_from_hw_enabled_state()
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c538 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; in split_stream_across_pipes()