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Searched refs:hw_ps (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu10_hwmgr.c84 static struct smu10_power_state *cast_smu10_ps(struct pp_hw_power_state *hw_ps) in cast_smu10_ps() argument
86 if (SMU10_Magic != hw_ps->magic) in cast_smu10_ps()
89 return (struct smu10_power_state *)hw_ps; in cast_smu10_ps()
93 const struct pp_hw_power_state *hw_ps) in cast_const_smu10_ps() argument
95 if (SMU10_Magic != hw_ps->magic) in cast_const_smu10_ps()
98 return (struct smu10_power_state *)hw_ps; in cast_const_smu10_ps()
800 struct pp_hw_power_state *hw_ps) in smu10_dpm_patch_boot_state() argument
807 struct pp_hw_power_state *hw_ps, in smu10_dpm_get_pp_table_entry_callback() argument
811 struct smu10_power_state *smu10_ps = cast_smu10_ps(hw_ps); in smu10_dpm_get_pp_table_entry_callback()
Dprocesspptables.h35 struct pp_hw_power_state *hw_ps,
Dsmu8_hwmgr.c51 static struct smu8_power_state *cast_smu8_power_state(struct pp_hw_power_state *hw_ps) in cast_smu8_power_state() argument
53 if (smu8_magic != hw_ps->magic) in cast_smu8_power_state()
56 return (struct smu8_power_state *)hw_ps; in cast_smu8_power_state()
60 const struct pp_hw_power_state *hw_ps) in cast_const_smu8_power_state() argument
62 if (smu8_magic != hw_ps->magic) in cast_const_smu8_power_state()
65 return (struct smu8_power_state *)hw_ps; in cast_const_smu8_power_state()
1349 struct pp_hw_power_state *hw_ps) in smu8_dpm_patch_boot_state() argument
1352 struct smu8_power_state *smu8_ps = cast_smu8_power_state(hw_ps); in smu8_dpm_patch_boot_state()
1364 struct pp_hw_power_state *hw_ps, in smu8_dpm_get_pp_table_entry_callback() argument
1368 struct smu8_power_state *smu8_ps = cast_smu8_power_state(hw_ps); in smu8_dpm_get_pp_table_entry_callback()
Dsmu7_hwmgr.c117 struct pp_hw_power_state *hw_ps) in cast_phw_smu7_power_state() argument
119 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), in cast_phw_smu7_power_state()
123 return (struct smu7_power_state *)hw_ps; in cast_phw_smu7_power_state()
127 const struct pp_hw_power_state *hw_ps) in cast_const_phw_smu7_power_state() argument
129 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), in cast_const_phw_smu7_power_state()
133 return (const struct smu7_power_state *)hw_ps; in cast_const_phw_smu7_power_state()
3157 struct pp_hw_power_state *hw_ps) in smu7_dpm_patch_boot_state() argument
3160 struct smu7_power_state *ps = (struct smu7_power_state *)hw_ps; in smu7_dpm_patch_boot_state()
Dvega10_hwmgr.c97 struct pp_hw_power_state *hw_ps) in cast_phw_vega10_power_state() argument
99 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic), in cast_phw_vega10_power_state()
103 return (struct vega10_power_state *)hw_ps; in cast_phw_vega10_power_state()
107 const struct pp_hw_power_state *hw_ps) in cast_const_phw_vega10_power_state() argument
109 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic), in cast_const_phw_vega10_power_state()
113 return (const struct vega10_power_state *)hw_ps; in cast_const_phw_vega10_power_state()
3225 struct pp_hw_power_state *hw_ps) in vega10_patch_boot_state() argument
Dvega12_hwmgr.c1085 struct pp_hw_power_state *hw_ps) in vega12_patch_boot_state() argument
/drivers/staging/media/rkvdec/
Drkvdec-h264.c645 struct rkvdec_sps_pps_packet *hw_ps; in assemble_hw_pps() local
656 hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; in assemble_hw_pps()
657 memset(hw_ps, 0, sizeof(*hw_ps)); in assemble_hw_pps()
659 #define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value) in assemble_hw_pps()
/drivers/gpu/drm/amd/pm/inc/
Dhwmgr.h256 struct pp_hw_power_state *hw_ps);