| /drivers/iio/buffer/ |
| D | industrialio-hw-consumer.c | 53 struct iio_hw_consumer *hwc, struct iio_dev *indio_dev) in iio_hw_consumer_get_buffer() argument
58 list_for_each_entry(buf, &hwc->buffers, head) { in iio_hw_consumer_get_buffer()
72 list_add_tail(&buf->head, &hwc->buffers); in iio_hw_consumer_get_buffer()
86 struct iio_hw_consumer *hwc; in iio_hw_consumer_alloc() local
90 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL); in iio_hw_consumer_alloc()
91 if (!hwc) in iio_hw_consumer_alloc()
94 INIT_LIST_HEAD(&hwc->buffers); in iio_hw_consumer_alloc()
96 hwc->channels = iio_channel_get_all(dev); in iio_hw_consumer_alloc()
97 if (IS_ERR(hwc->channels)) { in iio_hw_consumer_alloc()
98 ret = PTR_ERR(hwc->channels); in iio_hw_consumer_alloc()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_pmu.c | 48 struct hw_perf_event *hwc = &event->hw; in amdgpu_perf_event_init() local
55 hwc->config = event->attr.config; in amdgpu_perf_event_init()
63 struct hw_perf_event *hwc = &event->hw; in amdgpu_perf_start() local
68 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED))) in amdgpu_perf_start()
71 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); in amdgpu_perf_start()
72 hwc->state = 0; in amdgpu_perf_start()
77 pe->adev->df.funcs->pmc_start(pe->adev, hwc->config, 1); in amdgpu_perf_start()
79 pe->adev->df.funcs->pmc_start(pe->adev, hwc->config, 0); in amdgpu_perf_start()
92 struct hw_perf_event *hwc = &event->hw; in amdgpu_perf_read() local
100 prev = local64_read(&hwc->prev_count); in amdgpu_perf_read()
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| /drivers/perf/hisilicon/ |
| D | hisi_uncore_pmu.c | 134 struct hw_perf_event *hwc = &event->hw; in hisi_uncore_pmu_event_init() local
173 hwc->idx = -1; in hisi_uncore_pmu_event_init()
174 hwc->config_base = event->attr.config; in hisi_uncore_pmu_event_init()
190 struct hw_perf_event *hwc = &event->hw; in hisi_uncore_pmu_enable_event() local
192 hisi_pmu->ops->write_evtype(hisi_pmu, hwc->idx, in hisi_uncore_pmu_enable_event()
195 hisi_pmu->ops->enable_counter_int(hisi_pmu, hwc); in hisi_uncore_pmu_enable_event()
196 hisi_pmu->ops->enable_counter(hisi_pmu, hwc); in hisi_uncore_pmu_enable_event()
205 struct hw_perf_event *hwc = &event->hw; in hisi_uncore_pmu_disable_event() local
207 hisi_pmu->ops->disable_counter(hisi_pmu, hwc); in hisi_uncore_pmu_disable_event()
208 hisi_pmu->ops->disable_counter_int(hisi_pmu, hwc); in hisi_uncore_pmu_disable_event()
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| D | hisi_uncore_ddrc_pmu.c | 47 #define GET_DDRC_EVENTID(hwc) (hwc->config_base & 0x7) argument
65 struct hw_perf_event *hwc) in hisi_ddrc_pmu_read_counter() argument
68 u32 idx = GET_DDRC_EVENTID(hwc); in hisi_ddrc_pmu_read_counter()
79 struct hw_perf_event *hwc, u64 val) in hisi_ddrc_pmu_write_counter() argument
81 u32 idx = GET_DDRC_EVENTID(hwc); in hisi_ddrc_pmu_write_counter()
122 struct hw_perf_event *hwc) in hisi_ddrc_pmu_enable_counter() argument
128 val |= (1 << GET_DDRC_EVENTID(hwc)); in hisi_ddrc_pmu_enable_counter()
133 struct hw_perf_event *hwc) in hisi_ddrc_pmu_disable_counter() argument
139 val &= ~(1 << GET_DDRC_EVENTID(hwc)); in hisi_ddrc_pmu_disable_counter()
147 struct hw_perf_event *hwc = &event->hw; in hisi_ddrc_pmu_get_event_idx() local
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| D | hisi_uncore_hha_pmu.c | 51 struct hw_perf_event *hwc) in hisi_hha_pmu_read_counter() argument
53 u32 idx = hwc->idx; in hisi_hha_pmu_read_counter()
65 struct hw_perf_event *hwc, u64 val) in hisi_hha_pmu_write_counter() argument
67 u32 idx = hwc->idx; in hisi_hha_pmu_write_counter()
128 struct hw_perf_event *hwc) in hisi_hha_pmu_enable_counter() argument
134 val |= (1 << hwc->idx); in hisi_hha_pmu_enable_counter()
139 struct hw_perf_event *hwc) in hisi_hha_pmu_disable_counter() argument
145 val &= ~(1 << hwc->idx); in hisi_hha_pmu_disable_counter()
150 struct hw_perf_event *hwc) in hisi_hha_pmu_enable_counter_int() argument
156 val &= ~(1 << hwc->idx); in hisi_hha_pmu_enable_counter_int()
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| D | hisi_uncore_l3c_pmu.c | 50 struct hw_perf_event *hwc) in hisi_l3c_pmu_read_counter() argument
52 u32 idx = hwc->idx; in hisi_l3c_pmu_read_counter()
64 struct hw_perf_event *hwc, u64 val) in hisi_l3c_pmu_write_counter() argument
66 u32 idx = hwc->idx; in hisi_l3c_pmu_write_counter()
127 struct hw_perf_event *hwc) in hisi_l3c_pmu_enable_counter() argument
133 val |= (1 << hwc->idx); in hisi_l3c_pmu_enable_counter()
138 struct hw_perf_event *hwc) in hisi_l3c_pmu_disable_counter() argument
144 val &= ~(1 << hwc->idx); in hisi_l3c_pmu_disable_counter()
149 struct hw_perf_event *hwc) in hisi_l3c_pmu_enable_counter_int() argument
155 val &= ~(1 << hwc->idx); in hisi_l3c_pmu_enable_counter_int()
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| /drivers/perf/ |
| D | thunderx2_pmu.c | 325 struct hw_perf_event *hwc = &event->hw; in init_cntr_base_l3c() local
332 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_l3c()
334 hwc->event_base = (unsigned long)tx2_pmu->base in init_cntr_base_l3c()
341 struct hw_perf_event *hwc = &event->hw; in init_cntr_base_dmc() local
347 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_dmc()
350 hwc->event_base = (unsigned long)tx2_pmu->base in init_cntr_base_dmc()
357 struct hw_perf_event *hwc = &event->hw; in init_cntr_base_ccpi2() local
362 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_ccpi2()
364 hwc->event_base = (unsigned long)tx2_pmu->base; in init_cntr_base_ccpi2()
370 struct hw_perf_event *hwc = &event->hw; in uncore_start_event_l3c() local
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| D | arm_pmu.c | 199 struct hw_perf_event *hwc = &event->hw; in armpmu_event_set_period() local
200 s64 left = local64_read(&hwc->period_left); in armpmu_event_set_period()
201 s64 period = hwc->sample_period; in armpmu_event_set_period()
208 local64_set(&hwc->period_left, left); in armpmu_event_set_period()
209 hwc->last_period = period; in armpmu_event_set_period()
215 local64_set(&hwc->period_left, left); in armpmu_event_set_period()
216 hwc->last_period = period; in armpmu_event_set_period()
229 local64_set(&hwc->prev_count, (u64)-left); in armpmu_event_set_period()
241 struct hw_perf_event *hwc = &event->hw; in armpmu_event_update() local
246 prev_raw_count = local64_read(&hwc->prev_count); in armpmu_event_update()
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| D | qcom_l2_pmu.c | 299 struct hw_perf_event *hwc = &event->hw; in l2_cache_event_update() local
301 u32 idx = hwc->idx; in l2_cache_event_update()
304 prev = local64_read(&hwc->prev_count); in l2_cache_event_update()
306 } while (local64_cmpxchg(&hwc->prev_count, prev, now) != prev); in l2_cache_event_update()
320 struct hw_perf_event *hwc) in l2_cache_cluster_set_period() argument
322 u32 idx = hwc->idx; in l2_cache_cluster_set_period()
335 local64_set(&hwc->prev_count, new); in l2_cache_cluster_set_period()
342 struct hw_perf_event *hwc = &event->hw; in l2_cache_get_event_idx() local
347 if (hwc->config_base == L2CYCLE_CTR_RAW_CODE) { in l2_cache_get_event_idx()
364 group = L2_EVT_GROUP(hwc->config_base); in l2_cache_get_event_idx()
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| D | arm_smmuv3_pmu.c | 235 struct hw_perf_event *hwc = &event->hw; in smmu_pmu_event_update() local
238 u32 idx = hwc->idx; in smmu_pmu_event_update()
241 prev = local64_read(&hwc->prev_count); in smmu_pmu_event_update()
243 } while (local64_cmpxchg(&hwc->prev_count, prev, now) != prev); in smmu_pmu_event_update()
253 struct hw_perf_event *hwc) in smmu_pmu_set_period() argument
255 u32 idx = hwc->idx; in smmu_pmu_set_period()
278 local64_set(&hwc->prev_count, new); in smmu_pmu_set_period()
376 struct hw_perf_event *hwc = &event->hw; in smmu_pmu_event_init() local
386 if (hwc->sample_period) { in smmu_pmu_event_init()
424 hwc->idx = -1; in smmu_pmu_event_init()
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| D | fsl_imx8_ddr_perf.c | 321 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_init() local
360 hwc->idx = -1; in ddr_perf_event_init()
369 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_update() local
371 int counter = hwc->idx; in ddr_perf_event_update()
374 prev_raw_count = local64_read(&hwc->prev_count); in ddr_perf_event_update()
376 } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, in ddr_perf_event_update()
411 struct hw_perf_event *hwc = &event->hw; in ddr_perf_event_start() local
412 int counter = hwc->idx; in ddr_perf_event_start()
414 local64_set(&hwc->prev_count, 0); in ddr_perf_event_start()
422 hwc->state = 0; in ddr_perf_event_start()
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| D | arm-cci.c | 985 struct hw_perf_event *hwc = &event->hw; in pmu_event_update() local
989 prev_raw_count = local64_read(&hwc->prev_count); in pmu_event_update()
991 } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, in pmu_event_update()
1008 struct hw_perf_event *hwc = &event->hw; in pmu_event_set_period() local
1016 local64_set(&hwc->prev_count, val); in pmu_event_set_period()
1024 hwc->state |= PERF_HES_ARCH; in pmu_event_set_period()
1137 struct hw_perf_event *hwc = &event->hw; in cci_pmu_start() local
1138 int idx = hwc->idx; in cci_pmu_start()
1146 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); in cci_pmu_start()
1148 hwc->state = 0; in cci_pmu_start()
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| D | qcom_l3_pmu.c | 481 struct hw_perf_event *hwc = &event->hw; in qcom_l3_cache__event_init() local
492 if (hwc->sample_period) in qcom_l3_cache__event_init()
506 hwc->idx = -1; in qcom_l3_cache__event_init()
526 struct hw_perf_event *hwc = &event->hw; in qcom_l3_cache__event_start() local
529 hwc->state = 0; in qcom_l3_cache__event_start()
535 struct hw_perf_event *hwc = &event->hw; in qcom_l3_cache__event_stop() local
538 if (hwc->state & PERF_HES_STOPPED) in qcom_l3_cache__event_stop()
544 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; in qcom_l3_cache__event_stop()
550 struct hw_perf_event *hwc = &event->hw; in qcom_l3_cache__event_add() local
562 hwc->idx = idx; in qcom_l3_cache__event_add()
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| D | arm_dsu_pmu.c | 352 struct hw_perf_event *hwc = &event->hw; in dsu_pmu_event_update() local
357 prev_count = local64_read(&hwc->prev_count); in dsu_pmu_event_update()
359 } while (local64_cmpxchg(&hwc->prev_count, prev_count, new_count) != in dsu_pmu_event_update()
361 delta = (new_count - prev_count) & DSU_PMU_COUNTER_MASK(hwc->idx); in dsu_pmu_event_update()
445 struct hw_perf_event *hwc = &event->hw; in dsu_pmu_add() local
456 hwc->idx = idx; in dsu_pmu_add()
458 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; in dsu_pmu_add()
471 struct hw_perf_event *hwc = &event->hw; in dsu_pmu_del() local
472 int idx = hwc->idx; in dsu_pmu_del()
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| D | arm_spe_pmu.c | 734 struct hw_perf_event *hwc = &event->hw; in arm_spe_pmu_start() local
737 hwc->state = 0; in arm_spe_pmu_start()
739 if (hwc->state) in arm_spe_pmu_start()
755 reg = local64_read(&hwc->period_left); in arm_spe_pmu_start()
767 struct hw_perf_event *hwc = &event->hw; in arm_spe_pmu_stop() local
771 if (hwc->state & PERF_HES_STOPPED) in arm_spe_pmu_stop()
798 local64_set(&hwc->period_left, read_sysreg_s(SYS_PMSICR_EL1)); in arm_spe_pmu_stop()
799 hwc->state |= PERF_HES_UPTODATE; in arm_spe_pmu_stop()
802 hwc->state |= PERF_HES_STOPPED; in arm_spe_pmu_stop()
809 struct hw_perf_event *hwc = &event->hw; in arm_spe_pmu_add() local
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| /drivers/clk/ |
| D | clk-qoriq.c | 826 struct mux_hwclock *hwc = to_mux_hwclock(hw); in mux_set_parent() local
829 if (idx >= hwc->num_parents) in mux_set_parent()
832 clksel = hwc->parent_to_clksel[idx]; in mux_set_parent()
833 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); in mux_set_parent()
840 struct mux_hwclock *hwc = to_mux_hwclock(hw); in mux_get_parent() local
844 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in mux_get_parent()
846 ret = hwc->clksel_to_parent[clksel]; in mux_get_parent()
848 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg); in mux_get_parent()
869 struct mux_hwclock *hwc, in get_pll_div() argument
874 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) in get_pll_div()
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| /drivers/fpga/ |
| D | dfl-fme-perf.c | 798 struct hw_perf_event *hwc = &event->hw; in fme_perf_event_init() local
826 hwc->event_base = evtype; in fme_perf_event_init()
827 hwc->idx = (int)eventid; in fme_perf_event_init()
828 hwc->config_base = portid; in fme_perf_event_init()
846 struct hw_perf_event *hwc = &event->hw; in fme_perf_event_update() local
849 now = ops->read_counter(priv, (u32)hwc->idx, hwc->config_base); in fme_perf_event_update()
850 prev = local64_read(&hwc->prev_count); in fme_perf_event_update()
860 struct hw_perf_event *hwc = &event->hw; in fme_perf_event_start() local
863 count = ops->read_counter(priv, (u32)hwc->idx, hwc->config_base); in fme_perf_event_start()
864 local64_set(&hwc->prev_count, count); in fme_perf_event_start()
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| /drivers/iio/adc/ |
| D | stm32-dfsdm-adc.c | 79 struct iio_hw_consumer *hwc; member
1010 if (adc->hwc) { in stm32_dfsdm_postenable()
1011 ret = iio_hw_consumer_enable(adc->hwc); in stm32_dfsdm_postenable()
1039 if (adc->hwc) in stm32_dfsdm_postenable()
1040 iio_hw_consumer_disable(adc->hwc); in stm32_dfsdm_postenable()
1055 if (adc->hwc) in stm32_dfsdm_predisable()
1056 iio_hw_consumer_disable(adc->hwc); in stm32_dfsdm_predisable()
1234 ret = iio_hw_consumer_enable(adc->hwc); in stm32_dfsdm_read_raw()
1243 iio_hw_consumer_disable(adc->hwc); in stm32_dfsdm_read_raw()
1454 adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev); in stm32_dfsdm_adc_init()
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| /drivers/video/fbdev/ |
| D | au1200fb.c | 879 lcd->hwc.cursorctrl = 0; in au1200_setpanel()
880 lcd->hwc.cursorpos = 0; in au1200_setpanel()
881 lcd->hwc.cursorcolor0 = 0; in au1200_setpanel()
882 lcd->hwc.cursorcolor1 = 0; in au1200_setpanel()
883 lcd->hwc.cursorcolor2 = 0; in au1200_setpanel()
884 lcd->hwc.cursorcolor3 = 0; in au1200_setpanel()
928 D(lcd->hwc.cursorctrl); in au1200_setpanel()
929 D(lcd->hwc.cursorpos); in au1200_setpanel()
930 D(lcd->hwc.cursorcolor0); in au1200_setpanel()
931 D(lcd->hwc.cursorcolor1); in au1200_setpanel()
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| D | pxa168fb.h | 309 #define CFG_CSB_256x32(hwc) ((hwc) << 15) /* HWC */ argument
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| D | au1200fb.h | 59 } hwc; member
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| /drivers/hwtracing/coresight/ |
| D | coresight-etm-perf.c | 532 struct hw_perf_event *hwc = &event->hw; in etm_event_add() local
536 if (hwc->state & PERF_HES_STOPPED) in etm_event_add()
539 hwc->state = PERF_HES_STOPPED; in etm_event_add()
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| /drivers/gpu/drm/i915/ |
| D | i915_pmu.c | 609 struct hw_perf_event *hwc = &event->hw; in i915_pmu_event_read() local
613 prev = local64_read(&hwc->prev_count); in i915_pmu_event_read()
616 if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev) in i915_pmu_event_read()
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| /drivers/video/fbdev/mmp/hw/ |
| D | mmp_ctrl.h | 534 #define CFG_CSB_256x32(hwc) ((hwc)<<15) /* HWC */ argument
|