| /drivers/i2c/busses/ |
| D | i2c-sh7760.c | 114 struct cami2c *id = ptr; in sh7760_i2c_irq() local
115 struct i2c_msg *msg = id->msg; in sh7760_i2c_irq()
119 msr = IN32(id, I2CMSR); in sh7760_i2c_irq()
120 fsr = IN32(id, I2CFSR); in sh7760_i2c_irq()
124 OUT32(id, I2CMCR, 0); in sh7760_i2c_irq()
125 OUT32(id, I2CSCR, 0); in sh7760_i2c_irq()
126 OUT32(id, I2CSAR, 0); in sh7760_i2c_irq()
127 id->status |= IDS_DONE | IDS_ARBLOST; in sh7760_i2c_irq()
139 OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST); in sh7760_i2c_irq()
140 OUT32(id, I2CMCR, MCR_MIE | MCR_FSB); in sh7760_i2c_irq()
[all …]
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| D | i2c-cadence.c | 131 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
132 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
226 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id) in cdns_i2c_clear_bus_hold() argument
233 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround) in cdns_is_holdquirk() argument
236 (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1)); in cdns_is_holdquirk()
240 static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id) in cdns_i2c_set_mode() argument
249 id->dev_mode = mode; in cdns_i2c_set_mode()
250 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; in cdns_i2c_set_mode()
255 cdns_i2c_writereg(id->ctrl_reg_diva_divb | in cdns_i2c_set_mode()
268 cdns_i2c_writereg(id->ctrl_reg_diva_divb & in cdns_i2c_set_mode()
[all …]
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| /drivers/clk/at91/ |
| D | sam9x60.c | 77 u8 id; member
79 { .n = "ddrck", .p = "masterck", .id = 2 },
80 { .n = "uhpck", .p = "usbck", .id = 6 },
81 { .n = "pck0", .p = "prog0", .id = 8 },
82 { .n = "pck1", .p = "prog1", .id = 9 },
83 { .n = "qspick", .p = "masterck", .id = 19 },
88 u8 id; member
90 { .n = "pioA_clk", .id = 2, },
91 { .n = "pioB_clk", .id = 3, },
92 { .n = "pioC_clk", .id = 4, },
[all …]
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| D | sama5d4.c | 40 u8 id; member
42 { .n = "ddrck", .p = "masterck", .id = 2 },
43 { .n = "lcdck", .p = "masterck", .id = 3 },
44 { .n = "smdck", .p = "smdclk", .id = 4 },
45 { .n = "uhpck", .p = "usbck", .id = 6 },
46 { .n = "udpck", .p = "usbck", .id = 7 },
47 { .n = "pck0", .p = "prog0", .id = 8 },
48 { .n = "pck1", .p = "prog1", .id = 9 },
49 { .n = "pck2", .p = "prog2", .id = 10 },
54 u8 id; member
[all …]
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| D | at91sam9260.c | 13 u8 id; member
18 u8 id; member
74 { .n = "uhpck", .p = "usbck", .id = 6 },
75 { .n = "udpck", .p = "usbck", .id = 7 },
76 { .n = "pck0", .p = "prog0", .id = 8 },
77 { .n = "pck1", .p = "prog1", .id = 9 },
81 { .n = "pioA_clk", .id = 2 },
82 { .n = "pioB_clk", .id = 3 },
83 { .n = "pioC_clk", .id = 4 },
84 { .n = "adc_clk", .id = 5 },
[all …]
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| D | sama5d2.c | 41 u8 id; member
43 { .n = "ddrck", .p = "masterck", .id = 2 },
44 { .n = "lcdck", .p = "masterck", .id = 3 },
45 { .n = "uhpck", .p = "usbck", .id = 6 },
46 { .n = "udpck", .p = "usbck", .id = 7 },
47 { .n = "pck0", .p = "prog0", .id = 8 },
48 { .n = "pck1", .p = "prog1", .id = 9 },
49 { .n = "pck2", .p = "prog2", .id = 10 },
50 { .n = "iscck", .p = "masterck", .id = 18 },
55 u8 id; member
[all …]
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| D | sama5d3.c | 41 u8 id; member
43 { .n = "ddrck", .p = "masterck", .id = 2 },
44 { .n = "lcdck", .p = "masterck", .id = 3 },
45 { .n = "smdck", .p = "smdclk", .id = 4 },
46 { .n = "uhpck", .p = "usbck", .id = 6 },
47 { .n = "udpck", .p = "usbck", .id = 7 },
48 { .n = "pck0", .p = "prog0", .id = 8 },
49 { .n = "pck1", .p = "prog1", .id = 9 },
50 { .n = "pck2", .p = "prog2", .id = 10 },
55 u8 id; member
[all …]
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| D | sama7g5.c | 224 u8 id; member
228 .id = 1,
236 .id = 2,
244 .id = 3,
251 .id = 4,
268 u8 id; member
270 { .n = "pck0", .p = "prog0", .id = 8, },
271 { .n = "pck1", .p = "prog1", .id = 9, },
272 { .n = "pck2", .p = "prog2", .id = 10, },
273 { .n = "pck3", .p = "prog3", .id = 11, },
[all …]
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| D | at91sam9x5.c | 42 u8 id; member
44 { .n = "ddrck", .p = "masterck", .id = 2 },
45 { .n = "smdck", .p = "smdclk", .id = 4 },
46 { .n = "uhpck", .p = "usbck", .id = 6 },
47 { .n = "udpck", .p = "usbck", .id = 7 },
48 { .n = "pck0", .p = "prog0", .id = 8 },
49 { .n = "pck1", .p = "prog1", .id = 9 },
61 u8 id; member
65 { .n = "pioAB_clk", .id = 2, },
66 { .n = "pioCD_clk", .id = 3, },
[all …]
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| D | at91sam9g45.c | 41 u8 id; member
43 { .n = "ddrck", .p = "masterck", .id = 2 },
44 { .n = "uhpck", .p = "usbck", .id = 6 },
45 { .n = "pck0", .p = "prog0", .id = 8 },
46 { .n = "pck1", .p = "prog1", .id = 9 },
51 u8 id; member
55 { .n = "pioA_clk", .id = 2, },
56 { .n = "pioB_clk", .id = 3, },
57 { .n = "pioC_clk", .id = 4, },
58 { .n = "pioDE_clk", .id = 5, },
[all …]
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| D | at91rm9200.c | 13 u8 id; member
18 u8 id; member
41 { .n = "udpck", .p = "usbck", .id = 1 },
42 { .n = "uhpck", .p = "usbck", .id = 4 },
43 { .n = "pck0", .p = "prog0", .id = 8 },
44 { .n = "pck1", .p = "prog1", .id = 9 },
45 { .n = "pck2", .p = "prog2", .id = 10 },
46 { .n = "pck3", .p = "prog3", .id = 11 },
50 { .n = "pioA_clk", .id = 2 },
51 { .n = "pioB_clk", .id = 3 },
[all …]
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| D | at91sam9n12.c | 55 u8 id; member
57 { .n = "ddrck", .p = "masterck", .id = 2 },
58 { .n = "lcdck", .p = "masterck", .id = 3 },
59 { .n = "uhpck", .p = "usbck", .id = 6 },
60 { .n = "udpck", .p = "usbck", .id = 7 },
61 { .n = "pck0", .p = "prog0", .id = 8 },
62 { .n = "pck1", .p = "prog1", .id = 9 },
74 u8 id; member
78 { .n = "pioAB_clk", .id = 2, },
79 { .n = "pioCD_clk", .id = 3, },
[all …]
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| /drivers/gpu/drm/amd/display/dc/bios/ |
| D | bios_parser_common.c | 63 enum object_enum_id id; in enum_id_from_bios_object_id() local
67 id = ENUM_ID_1; in enum_id_from_bios_object_id()
70 id = ENUM_ID_2; in enum_id_from_bios_object_id()
73 id = ENUM_ID_3; in enum_id_from_bios_object_id()
76 id = ENUM_ID_4; in enum_id_from_bios_object_id()
79 id = ENUM_ID_5; in enum_id_from_bios_object_id()
82 id = ENUM_ID_6; in enum_id_from_bios_object_id()
85 id = ENUM_ID_7; in enum_id_from_bios_object_id()
88 id = ENUM_ID_UNKNOWN; in enum_id_from_bios_object_id()
92 return id; in enum_id_from_bios_object_id()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_link_encoder.h | 39 #define AUX_REG_LIST(id)\ argument
40 SRI(AUX_CONTROL, DP_AUX, id), \
41 SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
42 SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)
44 #define HPD_REG_LIST(id)\ argument
45 SRI(DC_HPD_CONTROL, HPD, id)
47 #define LE_COMMON_REG_LIST_BASE(id) \ argument
52 SRI(DIG_BE_CNTL, DIG, id), \
53 SRI(DIG_BE_EN_CNTL, DIG, id), \
54 SRI(DP_CONFIG, DP, id), \
[all …]
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| D | dce_transform.h | 38 #define XFM_COMMON_REG_LIST_DCE_BASE(id) \ argument
39 SRI(LB_DATA_FORMAT, LB, id), \
40 SRI(GAMUT_REMAP_CONTROL, DCP, id), \
41 SRI(GAMUT_REMAP_C11_C12, DCP, id), \
42 SRI(GAMUT_REMAP_C13_C14, DCP, id), \
43 SRI(GAMUT_REMAP_C21_C22, DCP, id), \
44 SRI(GAMUT_REMAP_C23_C24, DCP, id), \
45 SRI(GAMUT_REMAP_C31_C32, DCP, id), \
46 SRI(GAMUT_REMAP_C33_C34, DCP, id), \
47 SRI(OUTPUT_CSC_C11_C12, DCP, id), \
[all …]
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| /drivers/memory/tegra/ |
| D | tegra20.c | 12 .id = 0x00,
15 .id = 0x01,
18 .id = 0x02,
21 .id = 0x03,
24 .id = 0x04,
27 .id = 0x05,
30 .id = 0x06,
33 .id = 0x07,
36 .id = 0x08,
39 .id = 0x09,
[all …]
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| /drivers/media/platform/s3c-camif/ |
| D | camif-regs.h | 65 #define CIGCTRL_IRQ_CLR(id) BIT(19 - (id)) argument
71 #define S3C_CAMIF_REG_CIYSA(id, n) (0x18 + (id) * 0x54 + (n) * 4) argument
73 #define S3C_CAMIF_REG_CICBSA(id, n) (0x28 + (id) * 0x54 + (n) * 4) argument
75 #define S3C_CAMIF_REG_CICRSA(id, n) (0x38 + (id) * 0x54 + (n) * 4) argument
78 #define S3C_CAMIF_REG_CITRGFMT(id, _offs) (0x48 + (id) * (0x34 + (_offs))) argument
98 #define S3C_CAMIF_REG_CICTRL(id, _offs) (0x4c + (id) * (0x34 + (_offs))) argument
111 #define S3C_CAMIF_REG_CISCPRERATIO(id, _offs) (0x50 + (id) * (0x34 + (_offs))) argument
114 #define S3C_CAMIF_REG_CISCPREDST(id, _offs) (0x54 + (id) * (0x34 + (_offs))) argument
117 #define S3C_CAMIF_REG_CISCCTRL(id, _offs) (0x58 + (id) * (0x34 + (_offs))) argument
147 #define S3C_CAMIF_REG_CITAREA(id, _offs) (0x5c + (id) * (0x34 + (_offs))) argument
[all …]
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| /drivers/macintosh/ |
| D | adbhid.c | 212 int id; member
237 static void init_trackpad(int id);
238 static void init_trackball(int id);
239 static void init_turbomouse(int id);
240 static void init_microspeed(int id);
241 static void init_ms_a3(int id);
268 int id = (data[0] >> 4) & 0x0f; in adbhid_keyboard_input() local
270 if (!adbhid[id]) { in adbhid_keyboard_input()
272 id, data[0], data[1], data[2], data[3]); in adbhid_keyboard_input()
279 adbhid_input_keycode(id, data[1], 0); in adbhid_keyboard_input()
[all …]
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| /drivers/gpu/drm/msm/dsi/ |
| D | dsi_manager.c | 33 #define IS_MASTER_DSI_LINK(id) (msm_dsim_glb.master_dsi_link_id == id) argument
35 static inline struct msm_dsi *dsi_mgr_get_dsi(int id) in dsi_mgr_get_dsi() argument
37 return msm_dsim_glb.dsi[id]; in dsi_mgr_get_dsi()
40 static inline struct msm_dsi *dsi_mgr_get_other_dsi(int id) in dsi_mgr_get_other_dsi() argument
42 return msm_dsim_glb.dsi[(id + 1) % DSI_MAX]; in dsi_mgr_get_other_dsi()
45 static int dsi_mgr_parse_dual_dsi(struct device_node *np, int id) in dsi_mgr_parse_dual_dsi() argument
58 msm_dsim->master_dsi_link_id = id; in dsi_mgr_parse_dual_dsi()
67 static int dsi_mgr_setup_components(int id) in dsi_mgr_setup_components() argument
69 struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); in dsi_mgr_setup_components()
70 struct msm_dsi *other_dsi = dsi_mgr_get_other_dsi(id); in dsi_mgr_setup_components()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_dpp.h | 33 #define DPP_REG_LIST_DCN30_COMMON(id)\ argument
34 SRI(CM_DEALPHA, CM, id),\
35 SRI(CM_MEM_PWR_STATUS, CM, id),\
36 SRI(CM_BIAS_CR_R, CM, id),\
37 SRI(CM_BIAS_Y_G_CB_B, CM, id),\
38 SRI(PRE_DEGAM, CNVC_CFG, id),\
39 SRI(CM_GAMCOR_CONTROL, CM, id),\
40 SRI(CM_GAMCOR_LUT_CONTROL, CM, id),\
41 SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
42 SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
[all …]
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| /drivers/gpu/drm/amd/display/include/ |
| D | grph_object_id.h | 221 uint32_t id:8; member
230 uint32_t id, in dal_graphics_object_id_init() argument
235 id, enum_id, type, 0 in dal_graphics_object_id_init()
243 struct graphics_object_id id) in dal_graphics_object_id_to_uint() argument
245 return id.id + (id.enum_id << 0x8) + (id.type << 0xc); in dal_graphics_object_id_to_uint()
249 struct graphics_object_id id) in dal_graphics_object_id_get_controller_id() argument
251 if (id.type == OBJECT_TYPE_CONTROLLER) in dal_graphics_object_id_get_controller_id()
252 return (enum controller_id) id.id; in dal_graphics_object_id_get_controller_id()
257 struct graphics_object_id id) in dal_graphics_object_id_get_clock_source_id() argument
259 if (id.type == OBJECT_TYPE_CLOCK_SOURCE) in dal_graphics_object_id_get_clock_source_id()
[all …]
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| /drivers/gpu/host1x/hw/ |
| D | hw_host1x01_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r() argument
46 return 0x400 + id * REGISTER_STRIDE; in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
49 host1x_sync_syncpt_r(id)
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r() argument
52 return 0x40 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
55 host1x_sync_syncpt_thresh_cpu0_int_status_r(id)
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r() argument
58 return 0x60 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_disable_r()
[all …]
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| D | hw_host1x05_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r() argument
46 return 0xf80 + id * REGISTER_STRIDE; in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
49 host1x_sync_syncpt_r(id)
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r() argument
52 return 0xe80 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
55 host1x_sync_syncpt_thresh_cpu0_int_status_r(id)
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r() argument
58 return 0xf00 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_disable_r()
[all …]
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| D | hw_host1x04_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r() argument
46 return 0xf80 + id * REGISTER_STRIDE; in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
49 host1x_sync_syncpt_r(id)
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r() argument
52 return 0xe80 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
55 host1x_sync_syncpt_thresh_cpu0_int_status_r(id)
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r() argument
58 return 0xf00 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_disable_r()
[all …]
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| D | hw_host1x02_sync.h | 44 static inline u32 host1x_sync_syncpt_r(unsigned int id) in host1x_sync_syncpt_r() argument
46 return 0x400 + id * REGISTER_STRIDE; in host1x_sync_syncpt_r()
48 #define HOST1X_SYNC_SYNCPT(id) \ argument
49 host1x_sync_syncpt_r(id)
50 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) in host1x_sync_syncpt_thresh_cpu0_int_status_r() argument
52 return 0x40 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_cpu0_int_status_r()
54 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ argument
55 host1x_sync_syncpt_thresh_cpu0_int_status_r(id)
56 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) in host1x_sync_syncpt_thresh_int_disable_r() argument
58 return 0x60 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_disable_r()
[all …]
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