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Searched refs:inl (Results 1 – 25 of 112) sorted by relevance

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/drivers/staging/comedi/drivers/
Daddi_apci_1564.c176 inl(dev->iobase + APCI1564_DI_INT_STATUS_REG); in apci1564_reset()
214 status = inl(dev->iobase + APCI1564_DI_IRQ_REG); in apci1564_interrupt()
217 s->state = inl(dev->iobase + APCI1564_DI_INT_STATUS_REG); in apci1564_interrupt()
227 status = inl(devpriv->timer + ADDI_TCW_IRQ_REG); in apci1564_interrupt()
232 ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG); in apci1564_interrupt()
243 status = inl(iobase + ADDI_TCW_IRQ_REG); in apci1564_interrupt()
248 ctrl = inl(iobase + ADDI_TCW_CTRL_REG); in apci1564_interrupt()
268 data[1] = inl(dev->iobase + APCI1564_DI_REG); in apci1564_di_insn_bits()
278 s->state = inl(dev->iobase + APCI1564_DO_REG); in apci1564_do_insn_bits()
293 data[1] = inl(dev->iobase + APCI1564_DO_INT_STATUS_REG) & 3; in apci1564_diag_insn_bits()
[all …]
Dme4000.c329 val = inl(devpriv->plx_regbase + PLX9052_CNTRL); in me4000_xilinx_download()
338 val = inl(devpriv->plx_regbase + PLX9052_INTCSR); in me4000_xilinx_download()
345 val = inl(devpriv->plx_regbase + PLX9052_CNTRL); in me4000_xilinx_download()
361 val = inl(devpriv->plx_regbase + PLX9052_CNTRL); in me4000_xilinx_download()
370 val = inl(devpriv->plx_regbase + PLX9052_CNTRL); in me4000_xilinx_download()
378 val = inl(devpriv->plx_regbase + PLX9052_CNTRL); in me4000_xilinx_download()
390 ctrl = inl(dev->iobase + ME4000_AI_CTRL_REG); in me4000_ai_reset()
408 val = inl(devpriv->plx_regbase + PLX9052_CNTRL); in me4000_reset()
433 if (!(inl(dev->iobase + ME4000_DIO_DIR_REG) & 0x1)) in me4000_reset()
443 val = inl(dev->iobase + ME4000_AI_DATA_REG); in me4000_ai_get_sample()
[all …]
Daddi_apci_1032.c95 inl(dev->iobase + APCI1032_STATUS_REG); in apci1032_reset()
266 if ((inl(devpriv->amcc_iobase + AMCC_OP_REG_INTCSR) & in apci1032_interrupt()
271 ctrl = inl(dev->iobase + APCI1032_CTRL_REG); in apci1032_interrupt()
278 s->state = inl(dev->iobase + APCI1032_STATUS_REG) & 0xffff; in apci1032_interrupt()
294 data[1] = inl(dev->iobase + APCI1032_DI_REG); in apci1032_di_insn_bits()
Dadl_pci9118.c259 mcsr = inl(devpriv->iobase_a + AMCC_OP_REG_MCSR); in pci9118_amcc_dma_ena()
273 intcsr = inl(devpriv->iobase_a + AMCC_OP_REG_INTCSR); in pci9118_amcc_int_ena()
626 sampl = inl(dev->iobase + PCI9118_AI_FIFO_REG); in pci9118_ai_get_onesample()
689 intsrc = inl(dev->iobase + PCI9118_INT_CTRL_REG) & 0xf; in pci9118_interrupt()
690 intcsr = inl(devpriv->iobase_a + AMCC_OP_REG_INTCSR); in pci9118_interrupt()
709 adstat = inl(dev->iobase + PCI9118_AI_STATUS_REG); in pci9118_interrupt()
910 outl(inl(devpriv->iobase_a + AMCC_OP_REG_INTCSR) | EN_A2P_TRANSFERS, in pci9118_ai_setup_dma()
1115 inl(dev->iobase + PCI9118_AI_STATUS_REG); in pci9118_ai_cmd()
1116 inl(dev->iobase + PCI9118_INT_CTRL_REG); in pci9118_ai_cmd()
1309 status = inl(dev->iobase + PCI9118_AI_STATUS_REG); in pci9118_ai_eoc()
[all …]
Daddi_apci_2032.c48 s->state = inl(dev->iobase + APCI2032_DO_REG); in apci2032_do_insn_bits()
63 data[1] = inl(dev->iobase + APCI2032_INT_STATUS_REG) & 3; in apci2032_int_insn_bits()
174 val = inl(dev->iobase + APCI2032_STATUS_REG) & APCI2032_STATUS_IRQ; in apci2032_interrupt()
181 val = inl(dev->iobase + APCI2032_INT_STATUS_REG) & 3; in apci2032_interrupt()
Daddi_apci_3501.c100 status = inl(dev->iobase + APCI3501_AO_CTRL_STATUS_REG); in apci3501_wait_for_dac()
160 data[1] = inl(dev->iobase + APCI3501_DI_REG) & 0x3; in apci3501_di_insn_bits()
170 s->state = inl(dev->iobase + APCI3501_DO_REG); in apci3501_do_insn_bits()
/drivers/net/ethernet/mellanox/mlx4/
Den_tx.c295 if (!tx_info->inl) { in mlx4_en_free_tx_desc()
681 struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; in build_inline_wqe() local
682 int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof(*inl); in build_inline_wqe()
687 inl->byte_count = cpu_to_be32(1 << 31 | skb->len); in build_inline_wqe()
689 inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); in build_inline_wqe()
690 memset(((void *)(inl + 1)) + skb->len, 0, in build_inline_wqe()
693 skb_copy_from_linear_data(skb, inl + 1, hlen); in build_inline_wqe()
695 memcpy(((void *)(inl + 1)) + hlen, fragptr, in build_inline_wqe()
699 inl->byte_count = cpu_to_be32(1 << 31 | spc); in build_inline_wqe()
701 skb_copy_from_linear_data(skb, inl + 1, hlen); in build_inline_wqe()
[all …]
/drivers/leds/
Dleds-ss4200.c184 gpio_out = inl(nas_gpio_io_base + port); in __nasgpio_led_set_attr()
207 gpio_in = inl(nas_gpio_io_base + port); in nasgpio_led_get_attr()
282 config_data = inl(nas_gpio_io_base + GPIO_USE_SEL); in ich7_gpio_init()
286 config_data = inl(nas_gpio_io_base + GPIO_USE_SEL); in ich7_gpio_init()
295 config_data = inl(nas_gpio_io_base + GP_IO_SEL); in ich7_gpio_init()
301 config_data = inl(nas_gpio_io_base + GP_IO_SEL); in ich7_gpio_init()
308 config_data = inl(nas_gpio_io_base + GP_LVL); in ich7_gpio_init()
314 config_data = inl(nas_gpio_io_base + GPO_BLINK); in ich7_gpio_init()
320 config_data = inl(nas_gpio_io_base + GPI_INV); in ich7_gpio_init()
/drivers/watchdog/
DiTCO_vendor_support.c82 val32 = inl(smires->start); in supermicro_old_pre_start()
92 val32 = inl(smires->start); in supermicro_old_pre_stop()
132 val32 = inl(smires->start); in broken_bios_start()
143 val32 = inl(smires->start); in broken_bios_stop()
Dnv_tco.c81 val = inl(TCO_CNT(tcobase)); in tco_timer_start()
93 val = inl(TCO_CNT(tcobase)); in tco_timer_stop()
354 val = inl(MCP51_SMI_EN(tcobase)); in nv_tco_getdevice()
357 val = inl(MCP51_SMI_EN(tcobase)); in nv_tco_getdevice()
390 inl(TCO_STS(tcobase)) & TCO_STS_TCO2TO_STS ? "" : "not "); in nv_tco_init()
Die6xx_wdt.c184 inl(ie6xx_wdt_data.sch_wdtba + PV1)); in ie6xx_wdt_show()
186 inl(ie6xx_wdt_data.sch_wdtba + PV2)); in ie6xx_wdt_show()
192 inl(ie6xx_wdt_data.sch_wdtba + DCR)); in ie6xx_wdt_show()
/drivers/net/ethernet/dec/tulip/
Dde4x5.c687 imr = inl(DE4X5_IMR);\
698 imr = inl(DE4X5_IMR);\
707 omr = inl(DE4X5_OMR);\
713 omr = inl(DE4X5_OMR);\
1064 i=inl(DE4X5_BMR);\
1070 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1114 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) { in de4x5_hw_init()
1343 printk("\tsts: 0x%08x\n", inl(DE4X5_STS)); in de4x5_open()
1344 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR)); in de4x5_open()
1345 printk("\timr: 0x%08x\n", inl(DE4X5_IMR)); in de4x5_open()
[all …]
Dde4x5.h923 omr = inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX);\
931 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\
935 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\
950 omr = inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX);\
960 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\
964 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\
976 omr = (inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\
979 omr = (inl(DE4X5_OMR) & ~(OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\
982 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | OMR_FDX));\
/drivers/gpio/
Dgpio-vx855.c97 reg_out = inl(vg->io_gpo); in vx855gpio_direction_input()
112 reg_in = inl(vg->io_gpi); in vx855gpio_get()
118 reg_in = inl(vg->io_gpo); in vx855gpio_get()
122 reg_in = inl(vg->io_gpi); in vx855gpio_get()
142 reg_out = inl(vg->io_gpo); in vx855gpio_set()
Dgpio-cs5535.c76 val |= (inl(addr) & 0xffff); /* ignore the high bits */ in errata_outl()
78 val |= (inl(addr) ^ (val >> 16)); in errata_outl()
136 val = inl(chip->base + reg); in cs5535_gpio_isset()
139 val = inl(chip->base + 0x80 + reg); in cs5535_gpio_isset()
182 val = inl(chip->base + offset); in cs5535_gpio_setup_event()
/drivers/ide/
Dcs5530.c56 unsigned int format = (inl(basereg + 4) >> 31) & 1; in cs5530_set_pio_mode()
117 reg = inl(basereg + 4); /* get drive0 config register */ in cs5530_set_dma_mode()
235 d0_timings = inl(basereg + 0); in init_hwif_cs5530()
238 if (CS5530_BAD_PIO(inl(basereg + 8))) in init_hwif_cs5530()
/drivers/video/backlight/
Dcr_bllcd.c63 u32 cur = inl(addr); in cr_backlight_set_intensity()
81 u32 cur = inl(addr); in cr_backlight_get_intensity()
100 u32 cur = inl(addr); in cr_panel_on()
125 u32 cur = inl(addr); in cr_panel_off()
/drivers/platform/x86/
Dintel_int0002_vgpio.c90 gpe_en_reg = inl(GPE0A_EN_PORT); in int0002_irq_unmask()
99 gpe_en_reg = inl(GPE0A_EN_PORT); in int0002_irq_mask()
126 gpe_sts_reg = inl(GPE0A_STS_PORT); in int0002_irq()
142 gpe_sts_reg = inl(GPE0A_STS_PORT); in int0002_check_wake()
/drivers/infiniband/hw/mlx5/
Dwr.c486 int inl = 0; in set_data_inl_seg() local
497 inl += len; in set_data_inl_seg()
499 if (unlikely(inl > qp->max_inline_data)) in set_data_inl_seg()
521 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); in set_data_inl_seg()
523 *wqe_sz += ALIGN(inl + sizeof(seg->byte_count), 16) / 16; in set_data_inl_seg()
551 struct mlx5_bsf_inl *inl) in mlx5_fill_inl_bsf() argument
554 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | in mlx5_fill_inl_bsf()
556 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); in mlx5_fill_inl_bsf()
557 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); in mlx5_fill_inl_bsf()
559 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; in mlx5_fill_inl_bsf()
[all …]
/drivers/gpu/drm/gma500/
Dcdv_device.c218 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); in cdv_init_pm()
227 u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); in cdv_init_pm()
383 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); in cdv_power_down()
391 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); in cdv_power_down()
405 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); in cdv_power_up()
413 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); in cdv_power_up()
/drivers/scsi/
D3w-xxxx.c305 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev)); in tw_poll_status()
312 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev)); in tw_poll_status()
334 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev)); in tw_poll_status_gone()
341 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev)); in tw_poll_status_gone()
364 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev)); in tw_post_command_packet()
450 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev)); in tw_check_errors()
465 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev)); in tw_empty_response_que()
468 response_que_value = inl(TW_RESPONSE_QUEUE_REG_ADDR(tw_dev)); in tw_empty_response_que()
469 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev)); in tw_empty_response_que()
551 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev)); in tw_aen_read_queue()
[all …]
/drivers/platform/mips/
Drs780e-acpi.c69 outl(inl(ACPI_GPE0_BLK), ACPI_GPE0_BLK); in acpi_hw_clear_status()
103 value = inl(ACPI_GPE0_BLK + 4); in acpi_registers_setup()
/drivers/mtd/maps/
Dl440gx.c40 outl(inl(VPP_PORT) | 1, VPP_PORT); in l440gx_set_vpp()
43 outl(inl(VPP_PORT) & ~1, VPP_PORT); in l440gx_set_vpp()
/drivers/gpu/drm/vmwgfx/
Dvmwgfx_irq.c85 status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); in vmw_irq_handler()
336 status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); in vmw_irq_preinstall()
353 status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); in vmw_irq_uninstall()
/drivers/isdn/hardware/mISDN/
Davmfritz.c213 return 0xff & inl(fc->addr + AVM_ISACX_DATA); in ReadISAC_V2()
233 data[i] = 0xff & inl(fc->addr + AVM_ISACX_DATA); in ReadFiFoISAC_V2()
297 return inl(addr + CHIP_WINDOW + HDLC_STATUS); in __read_status_pci()
303 return inl(addr + (channel == 2 ? AVM_HDLC_STATUS_2 : in __read_status_pciv2()
421 val = le32_to_cpu(inl(addr)); in hdlc_empty_fifo()
964 val = inl(fc->addr); in setup_fritz()
966 ver = inl(fc->addr + CHIP_WINDOW + HDLC_STATUS) >> 24; in setup_fritz()
977 val = inl(fc->addr); in setup_fritz()
978 ver = inl(fc->addr + AVM_HDLC_STATUS_1) >> 24; in setup_fritz()

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