Home
last modified time | relevance | path

Searched refs:ixLCAC_MC3_OVR_SEL (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_6_0_d.h36 #define ixLCAC_MC3_OVR_SEL 0x0126 macro
Dsmu_8_0_d.h642 #define ixLCAC_MC3_OVR_SEL 0xd0208158 macro
Dsmu_7_0_0_d.h735 #define ixLCAC_MC3_OVR_SEL 0xc0400d58 macro
Dsmu_7_1_1_d.h1035 #define ixLCAC_MC3_OVR_SEL 0xc0400158 macro
Dsmu_7_0_1_d.h1225 #define ixLCAC_MC3_OVR_SEL 0xc0400d58 macro
Dsmu_7_1_3_d.h1118 #define ixLCAC_MC3_OVR_SEL 0xc0400158 macro
Dsmu_7_1_2_d.h1186 #define ixLCAC_MC3_OVR_SEL 0xc0400158 macro
Dsmu_7_1_0_d.h1254 #define ixLCAC_MC3_OVR_SEL 0xc0400d58 macro
/drivers/gpu/drm/amd/pm/powerplay/
Dkv_dpm.c550 WREG32_SMC(ixLCAC_MC3_OVR_SEL, 0);