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Searched refs:lb_interrupt_mask (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Ddce_v10_0.c2979 u32 lb_interrupt_mask; in dce_v10_0_set_crtc_vblank_interrupt_state() local
2988 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v10_0_set_crtc_vblank_interrupt_state()
2989 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, in dce_v10_0_set_crtc_vblank_interrupt_state()
2991 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v10_0_set_crtc_vblank_interrupt_state()
2994 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v10_0_set_crtc_vblank_interrupt_state()
2995 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, in dce_v10_0_set_crtc_vblank_interrupt_state()
2997 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v10_0_set_crtc_vblank_interrupt_state()
3008 u32 lb_interrupt_mask; in dce_v10_0_set_crtc_vline_interrupt_state() local
3017 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v10_0_set_crtc_vline_interrupt_state()
3018 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, in dce_v10_0_set_crtc_vline_interrupt_state()
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Ddce_v11_0.c3105 u32 lb_interrupt_mask; in dce_v11_0_set_crtc_vblank_interrupt_state() local
3114 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v11_0_set_crtc_vblank_interrupt_state()
3115 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, in dce_v11_0_set_crtc_vblank_interrupt_state()
3117 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v11_0_set_crtc_vblank_interrupt_state()
3120 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v11_0_set_crtc_vblank_interrupt_state()
3121 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, in dce_v11_0_set_crtc_vblank_interrupt_state()
3123 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); in dce_v11_0_set_crtc_vblank_interrupt_state()
3134 u32 lb_interrupt_mask; in dce_v11_0_set_crtc_vline_interrupt_state() local
3143 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); in dce_v11_0_set_crtc_vline_interrupt_state()
3144 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, in dce_v11_0_set_crtc_vline_interrupt_state()
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Ddce_v8_0.c2867 u32 reg_block, lb_interrupt_mask; in dce_v8_0_set_crtc_vblank_interrupt_state() local
2900 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); in dce_v8_0_set_crtc_vblank_interrupt_state()
2901 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK; in dce_v8_0_set_crtc_vblank_interrupt_state()
2902 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); in dce_v8_0_set_crtc_vblank_interrupt_state()
2905 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); in dce_v8_0_set_crtc_vblank_interrupt_state()
2906 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK; in dce_v8_0_set_crtc_vblank_interrupt_state()
2907 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); in dce_v8_0_set_crtc_vblank_interrupt_state()
2918 u32 reg_block, lb_interrupt_mask; in dce_v8_0_set_crtc_vline_interrupt_state() local
2951 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); in dce_v8_0_set_crtc_vline_interrupt_state()
2952 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK; in dce_v8_0_set_crtc_vline_interrupt_state()
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