| /drivers/gpu/drm/nouveau/ |
| D | nouveau_dp.c | 146 nv_encoder->dp.link_bw = 27000 * dpcd[DP_MAX_LINK_RATE]; in nouveau_dp_detect()
151 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, in nouveau_dp_detect()
155 nv_encoder->dcb->dpconf.link_bw); in nouveau_dp_detect()
159 if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw) in nouveau_dp_detect()
160 nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw; in nouveau_dp_detect()
163 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw); in nouveau_dp_detect()
246 max_rate = outp->dp.link_nr * outp->dp.link_bw; in nv50_dp_mode_valid()
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| D | nouveau_encoder.h | 67 int link_bw; member
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| D | nouveau_bios.c | 1474 entry->dpconf.link_bw = 162000; in parse_dcb20_entry()
1477 entry->dpconf.link_bw = 270000; in parse_dcb20_entry()
1480 entry->dpconf.link_bw = 540000; in parse_dcb20_entry()
1484 entry->dpconf.link_bw = 810000; in parse_dcb20_entry()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_dp_link_training.c | 158 u8 link_bw, rate_select; in intel_dp_link_training_clock_recovery() local
164 &link_bw, &rate_select); in intel_dp_link_training_clock_recovery()
177 if (!link_bw) { in intel_dp_link_training_clock_recovery()
188 if (link_bw) in intel_dp_link_training_clock_recovery()
190 "Using LINK_BW_SET value %02x\n", link_bw); in intel_dp_link_training_clock_recovery()
196 link_config[0] = link_bw; in intel_dp_link_training_clock_recovery()
203 if (!link_bw) in intel_dp_link_training_clock_recovery()
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| D | intel_dp.h | 101 u8 *link_bw, u8 *rate_select);
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| D | intel_display.h | 543 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
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| D | intel_dp.c | 1943 u8 *link_bw, u8 *rate_select) in intel_dp_compute_rate() argument
1947 *link_bw = 0; in intel_dp_compute_rate()
1951 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); in intel_dp_compute_rate()
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| D | intel_display.c | 7902 int lane, link_bw, fdi_dotclock, ret; in ilk_fdi_compute_config() local
7913 link_bw = intel_fdi_link_freq(i915, pipe_config); in ilk_fdi_compute_config()
7917 lane = ilk_get_lanes_required(fdi_dotclock, link_bw, in ilk_fdi_compute_config()
7923 link_bw, &pipe_config->fdi_m_n, false, false); in ilk_fdi_compute_config()
10236 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) in ilk_get_lanes_required() argument
10244 return DIV_ROUND_UP(bps, link_bw * 8); in ilk_get_lanes_required()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| D | dcb.c | 147 outp->dpconf.link_bw = 0x06; in dcb_outp_parse()
150 outp->dpconf.link_bw = 0x0a; in dcb_outp_parse()
153 outp->dpconf.link_bw = 0x14; in dcb_outp_parse()
157 outp->dpconf.link_bw = 0x1e; in dcb_outp_parse()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/i2c/ |
| D | anx9805.c | 193 int link_nr, int link_bw, bool enh) in anx9805_aux_lnk_ctl() argument
201 link_nr, link_bw, enh); in anx9805_aux_lnk_ctl()
203 nvkm_wri2cr(adap, aux->addr, 0xa0, link_bw); in anx9805_aux_lnk_ctl()
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| D | aux.h | 10 int (*lnk_ctl)(struct nvkm_i2c_aux *, int link_nr, int link_bw,
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| /drivers/gpu/drm/gma500/ |
| D | cdv_intel_dp.c | 265 uint8_t link_bw; member
360 cdv_intel_dp_link_clock(uint8_t link_bw) in cdv_intel_dp_link_clock() argument
362 if (link_bw == DP_LINK_BW_2_7) in cdv_intel_dp_link_clock()
920 intel_dp->link_bw = bws[clock]; in cdv_intel_dp_mode_fixup()
922 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw); in cdv_intel_dp_mode_fixup()
925 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
934 intel_dp->link_bw = bws[max_clock]; in cdv_intel_dp_mode_fixup()
935 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw); in cdv_intel_dp_mode_fixup()
938 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
1074 intel_dp->link_configuration[0] = intel_dp->link_bw; in cdv_intel_dp_mode_set()
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| /drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ |
| D | dcb.h | 49 int link_bw; member
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| /drivers/gpu/drm/nouveau/include/nvkm/subdev/ |
| D | i2c.h | 71 int nvkm_i2c_aux_lnk_ctl(struct nvkm_i2c_aux *, int link_nr, int link_bw,
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link_dp.c | 2378 uint32_t link_bw; in decide_dp_link_settings() local
2389 link_bw = dc_link_bandwidth_kbps( in decide_dp_link_settings()
2392 if (req_bw <= link_bw) { in decide_dp_link_settings()
2418 uint32_t link_bw; in decide_edp_link_settings() local
2440 link_bw = dc_link_bandwidth_kbps( in decide_edp_link_settings()
2443 if (req_bw <= link_bw) { in decide_edp_link_settings()
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| /drivers/gpu/drm/ |
| D | drm_dp_helper.c | 178 int drm_dp_bw_code_to_link_rate(u8 link_bw) in drm_dp_bw_code_to_link_rate() argument
181 return link_bw * 27000; in drm_dp_bw_code_to_link_rate()
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| /drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | dp.c | 351 const u8 outp_bw = dp->outp.info.dpconf.link_bw; in nvkm_dp_train()
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| /drivers/gpu/drm/nouveau/dispnv50/ |
| D | disp.c | 409 max_rate = nv_encoder->dp.link_nr * nv_encoder->dp.link_bw; in nv50_outp_atomic_fix_depth()
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