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Searched refs:m_reg (Results 1 – 22 of 22) sorted by relevance

/drivers/clk/qcom/
Dclk-pll.c88 regmap_read(pll->clkr.regmap, pll->m_reg, &m); in clk_pll_recalc_rate()
160 regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m); in clk_pll_set_rate()
225 regmap_write(regmap, pll->m_reg, config->m); in clk_pll_configure()
320 regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m); in clk_pll_sr2_set_rate()
Dclk-hfpll.h13 u32 m_reg; member
Dclk-pll.h41 u32 m_reg; member
Da53-pll.c61 pll->m_reg = 0x08; in qcom_a53pll_probe()
Dhfpll.c19 .m_reg = 0x08,
Dgcc-msm8960.c30 .m_reg = 0x3168,
57 .m_reg = 0x3148,
85 .m_reg = 0x320c,
111 .m_reg = 0x324c,
125 .m_reg = 0x330c,
151 .m_reg = 0x328c,
177 .m_reg = 0x32cc,
203 .m_reg = 0x330c,
217 .m_reg = 0x340c,
242 .m_reg = 0x31c8,
Dgcc-ipq806x.c30 .m_reg = 0x30c8,
57 .m_reg = 0x3168,
84 .m_reg = 0x3148,
112 .m_reg = 0x320c,
138 .m_reg = 0x324c,
164 .m_reg = 0x330c,
189 .m_reg = 0x31c8,
230 .m_reg = 0x31a8,
Dgcc-msm8939.c55 .m_reg = 0x21008,
86 .m_reg = 0x20008,
117 .m_reg = 0x4a008,
148 .m_reg = 0x23008,
179 .m_reg = 0x22008,
226 .m_reg = 0x24008,
272 .m_reg = 0x25008,
303 .m_reg = 0x37008,
Dclk-hfpll.c32 regmap_write(regmap, hd->m_reg, 0); in __clk_hfpll_init_once()
Dgcc-mdm9615.c42 .m_reg = 0x30c8,
80 .m_reg = 0x3148,
107 .m_reg = 0x31c8,
Dlcc-ipq806x.c28 .m_reg = 0x8,
Dmmcc-msm8974.c181 .m_reg = 0x0008,
208 .m_reg = 0x0048,
235 .m_reg = 0x4108,
250 .m_reg = 0x0088,
Dmmcc-apq8084.c216 .m_reg = 0x0008,
243 .m_reg = 0x0048,
270 .m_reg = 0x4108,
285 .m_reg = 0x0088,
301 .m_reg = 0x00a8,
Dlcc-msm8960.c28 .m_reg = 0x8,
Dlcc-mdm9615.c30 .m_reg = 0x8,
Dgcc-msm8916.c261 .m_reg = 0x21008,
288 .m_reg = 0x20008,
315 .m_reg = 0x4a008,
342 .m_reg = 0x23008,
Dgcc-msm8974.c59 .m_reg = 0x0008,
122 .m_reg = 0x0048,
149 .m_reg = 0x1dc8,
Dgcc-apq8084.c103 .m_reg = 0x0008,
166 .m_reg = 0x0048,
193 .m_reg = 0x1dc8,
Dmmcc-msm8960.c110 .m_reg = 0x324,
126 .m_reg = 0x340,
Dgcc-msm8660.c29 .m_reg = 0x3148,
Dgcc-qcs404.c385 .m_reg = 0x37008,
/drivers/video/fbdev/i810/
Di810_main.c708 u32 m_reg, n_reg, p_divisor, n_target_max; in i810_calc_dclk() local
729 n_reg = m_reg = n_target = 3; in i810_calc_dclk()
731 f_out = (p_divisor * n_reg * 1000000)/(4 * 24 * m_reg); in i810_calc_dclk()
732 mod = (p_divisor * n_reg * 1000000) % (4 * 24 * m_reg); in i810_calc_dclk()
733 m_target = m_reg; in i810_calc_dclk()
739 m_reg++; in i810_calc_dclk()