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Searched refs:mclk_mask (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c217 uint32_t *mclk_mask, in renoir_get_profiling_clk_mask() argument
225 if (mclk_mask) in renoir_get_profiling_clk_mask()
227 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1; in renoir_get_profiling_clk_mask()
233 if(mclk_mask) in renoir_get_profiling_clk_mask()
235 *mclk_mask = 0; in renoir_get_profiling_clk_mask()
250 uint32_t mclk_mask, soc_mask; in renoir_get_dpm_ultimate_freq() local
284 &mclk_mask, in renoir_get_dpm_ultimate_freq()
301 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); in renoir_get_dpm_ultimate_freq()
828 uint32_t sclk_mask, mclk_mask, soc_mask; in renoir_set_performance_level() local
895 &mclk_mask, in renoir_set_performance_level()
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/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega12_hwmgr.c1698 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega12_get_profiling_clk_mask() argument
1706 *mclk_mask = 0; in vega12_get_profiling_clk_mask()
1713 *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL; in vega12_get_profiling_clk_mask()
1720 *mclk_mask = 0; in vega12_get_profiling_clk_mask()
1723 *mclk_mask = mem_dpm_table->count - 1; in vega12_get_profiling_clk_mask()
1753 uint32_t mclk_mask = 0; in vega12_dpm_force_dpm_level() local
1770 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega12_dpm_force_dpm_level()
1774 vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); in vega12_dpm_force_dpm_level()
Dvega20_hwmgr.c2523 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega20_get_profiling_clk_mask() argument
2531 *mclk_mask = 0; in vega20_get_profiling_clk_mask()
2538 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL; in vega20_get_profiling_clk_mask()
2545 *mclk_mask = 0; in vega20_get_profiling_clk_mask()
2548 *mclk_mask = mem_dpm_table->count - 1; in vega20_get_profiling_clk_mask()
2723 uint32_t sclk_mask, mclk_mask, soc_mask; in vega20_dpm_force_dpm_level() local
2742 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega20_dpm_force_dpm_level()
2746 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); in vega20_dpm_force_dpm_level()
Dsmu7_hwmgr.c2826 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) in smu7_get_profiling_clk() argument
2844 *mclk_mask = golden_dpm_table->mclk_table.count - 1; in smu7_get_profiling_clk()
2847 *mclk_mask = golden_dpm_table->mclk_table.count - 2; in smu7_get_profiling_clk()
2889 *mclk_mask = 0; in smu7_get_profiling_clk()
2891 *mclk_mask = golden_dpm_table->mclk_table.count - 1; in smu7_get_profiling_clk()
2905 uint32_t mclk_mask = 0; in smu7_force_dpm_level() local
2909 smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); in smu7_force_dpm_level()
2925 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); in smu7_force_dpm_level()
2929 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); in smu7_force_dpm_level()
Dvega10_hwmgr.c4156 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega10_get_profiling_clk_mask() argument
4166 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL; in vega10_get_profiling_clk_mask()
4174 *mclk_mask = 0; in vega10_get_profiling_clk_mask()
4184 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1; in vega10_get_profiling_clk_mask()
4276 uint32_t mclk_mask = 0; in vega10_dpm_force_dpm_level() local
4280 vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4296 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4300 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); in vega10_dpm_force_dpm_level()