| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | smu7_hwmgr.c | 689 &data->dpm_table.mclk_table, in smu7_reset_dpm_tables()
757 data->dpm_table.mclk_table.count = 0; in smu7_setup_dpm_tables_v0()
759 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != in smu7_setup_dpm_tables_v0()
761 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = in smu7_setup_dpm_tables_v0()
763 …data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0; in smu7_setup_dpm_tables_v0()
764 data->dpm_table.mclk_table.count++; in smu7_setup_dpm_tables_v0()
852 data->dpm_table.mclk_table.count = 0; in smu7_setup_dpm_tables_v1()
854 if (i == 0 || data->dpm_table.mclk_table.dpm_levels in smu7_setup_dpm_tables_v1()
855 [data->dpm_table.mclk_table.count - 1].value != in smu7_setup_dpm_tables_v1()
857 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = in smu7_setup_dpm_tables_v1()
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| D | smu10_hwmgr.c | 892 struct smu10_voltage_dependency_table *mclk_table = in smu10_force_clock_level() local
922 if (low > mclk_table->count - 1 || high > mclk_table->count - 1) in smu10_force_clock_level()
927 mclk_table->entries[low].clk/100, in smu10_force_clock_level()
932 mclk_table->entries[high].clk/100, in smu10_force_clock_level()
947 struct smu10_voltage_dependency_table *mclk_table = in smu10_print_clock_levels() local
976 for (i = 0; i < mclk_table->count; i++) in smu10_print_clock_levels()
979 mclk_table->entries[i].clk / 100, in smu10_print_clock_levels()
980 ((mclk_table->entries[i].clk / 100) in smu10_print_clock_levels()
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| D | vega10_processpptables.c | 609 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; in get_mclk_voltage_dependency_table() local
618 mclk_table = kzalloc(table_size, GFP_KERNEL); in get_mclk_voltage_dependency_table()
620 if (!mclk_table) in get_mclk_voltage_dependency_table()
623 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; in get_mclk_voltage_dependency_table()
626 mclk_table->entries[i].vddInd = in get_mclk_voltage_dependency_table()
628 mclk_table->entries[i].vddciInd = in get_mclk_voltage_dependency_table()
630 mclk_table->entries[i].mvddInd = in get_mclk_voltage_dependency_table()
632 mclk_table->entries[i].clk = in get_mclk_voltage_dependency_table()
636 *pp_vega10_mclk_dep_table = mclk_table; in get_mclk_voltage_dependency_table()
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| D | vega10_hwmgr.c | 668 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = in vega10_patch_voltage_dependency_tables_with_lookup_table() local
695 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { in vega10_patch_voltage_dependency_tables_with_lookup_table()
696 voltage_id = mclk_table->entries[entry_id].vddInd; in vega10_patch_voltage_dependency_tables_with_lookup_table()
697 mclk_table->entries[entry_id].vddc = in vega10_patch_voltage_dependency_tables_with_lookup_table()
699 voltage_id = mclk_table->entries[entry_id].vddciInd; in vega10_patch_voltage_dependency_tables_with_lookup_table()
700 mclk_table->entries[entry_id].vddci = in vega10_patch_voltage_dependency_tables_with_lookup_table()
702 voltage_id = mclk_table->entries[entry_id].mvddInd; in vega10_patch_voltage_dependency_tables_with_lookup_table()
703 mclk_table->entries[entry_id].mvdd = in vega10_patch_voltage_dependency_tables_with_lookup_table()
3393 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); in vega10_find_dpm_states_clocks_in_dpm_table() local
3410 for (i = 0; i < mclk_table->count; i++) { in vega10_find_dpm_states_clocks_in_dpm_table()
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| D | process_pptables_v1_0.c | 374 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; in get_mclk_voltage_dependency_table() local
384 mclk_table = kzalloc(table_size, GFP_KERNEL); in get_mclk_voltage_dependency_table()
386 if (NULL == mclk_table) in get_mclk_voltage_dependency_table()
389 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; in get_mclk_voltage_dependency_table()
394 entries, mclk_table, i); in get_mclk_voltage_dependency_table()
405 *pp_tonga_mclk_dep_table = mclk_table; in get_mclk_voltage_dependency_table()
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| D | smu7_hwmgr.h | 105 struct smu7_single_dpm_table mclk_table; member
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| D | vega12_hwmgr.c | 2690 struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
2693 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
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| D | vega20_hwmgr.c | 1517 struct vega20_single_dpm_table *mclk_table = in vega20_get_mclk_od() local
1521 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; in vega20_get_mclk_od()
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| /drivers/gpu/drm/radeon/ |
| D | ci_dpm.c | 2541 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2544 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
3321 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
3322 if (dpm_table->mclk_table.dpm_levels[i].value == 0) in ci_populate_all_memory_levels()
3325 dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
3333 if ((dpm_table->mclk_table.count >= 2) && in ci_populate_all_memory_levels()
3343 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3345 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in ci_populate_all_memory_levels()
3347 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3452 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
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| D | ci_dpm.h | 70 struct ci_single_dpm_table mclk_table; member
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| /drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | iceland_smumgr.c | 1361 for (i = 0; i < dpm_table->mclk_table.count; i++) { in iceland_populate_all_memory_levels()
1362 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in iceland_populate_all_memory_levels()
1364 result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in iceland_populate_all_memory_levels()
1382 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in iceland_populate_all_memory_levels()
1383 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in iceland_populate_all_memory_levels()
1385 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in iceland_populate_all_memory_levels()
1622 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in iceland_program_memory_timing_parameters()
1625 data->dpm_table.mclk_table.dpm_levels[j].value, in iceland_program_memory_timing_parameters()
1667 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in iceland_populate_smc_boot_level()
1761 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { in iceland_convert_mc_reg_table_to_smc()
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| D | vegam_smumgr.c | 1050 for (i = 0; i < dpm_table->mclk_table.count; i++) { in vegam_populate_all_memory_levels()
1051 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in vegam_populate_all_memory_levels()
1055 dpm_table->mclk_table.dpm_levels[i].value, in vegam_populate_all_memory_levels()
1068 (uint8_t)dpm_table->mclk_table.count; in vegam_populate_all_memory_levels()
1070 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in vegam_populate_all_memory_levels()
1072 for (i = 0; i < dpm_table->mclk_table.count; i++) in vegam_populate_all_memory_levels()
1076 levels[dpm_table->mclk_table.count - 1].DisplayWatermark = in vegam_populate_all_memory_levels()
1289 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { in vegam_program_memory_timing_parameters()
1292 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in vegam_program_memory_timing_parameters()
1381 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in vegam_populate_smc_boot_level()
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| D | fiji_smumgr.c | 1235 for (i = 0; i < dpm_table->mclk_table.count; i++) { in fiji_populate_all_memory_levels()
1236 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in fiji_populate_all_memory_levels()
1240 dpm_table->mclk_table.dpm_levels[i].value, in fiji_populate_all_memory_levels()
1258 (uint8_t)dpm_table->mclk_table.count; in fiji_populate_all_memory_levels()
1260 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in fiji_populate_all_memory_levels()
1262 levels[dpm_table->mclk_table.count - 1].DisplayWatermark = in fiji_populate_all_memory_levels()
1375 data->dpm_table.mclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1396 data->dpm_table.mclk_table.dpm_levels[0].value, in fiji_populate_smc_acpi_level()
1534 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in fiji_program_memory_timing_parameters()
1537 data->dpm_table.mclk_table.dpm_levels[j].value, in fiji_program_memory_timing_parameters()
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| D | ci_smumgr.c | 1315 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
1316 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in ci_populate_all_memory_levels()
1318 result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
1328 if ((dpm_table->mclk_table.count >= 2) in ci_populate_all_memory_levels()
1338 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
1339 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in ci_populate_all_memory_levels()
1340 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in ci_populate_all_memory_levels()
1660 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in ci_program_memory_timing_parameters()
1663 data->dpm_table.mclk_table.dpm_levels[j].value, in ci_program_memory_timing_parameters()
1705 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in ci_populate_smc_boot_level()
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| D | polaris10_smumgr.c | 1140 for (i = 0; i < dpm_table->mclk_table.count; i++) { in polaris10_populate_all_memory_levels()
1141 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in polaris10_populate_all_memory_levels()
1145 dpm_table->mclk_table.dpm_levels[i].value, in polaris10_populate_all_memory_levels()
1147 if (i == dpm_table->mclk_table.count - 1) { in polaris10_populate_all_memory_levels()
1164 (uint8_t)dpm_table->mclk_table.count; in polaris10_populate_all_memory_levels()
1166 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in polaris10_populate_all_memory_levels()
1263 data->dpm_table.mclk_table.dpm_levels[0].value, in polaris10_populate_smc_acpi_level()
1372 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { in polaris10_program_memory_timing_parameters()
1375 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in polaris10_program_memory_timing_parameters()
1378 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j); in polaris10_program_memory_timing_parameters()
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| D | tonga_smumgr.c | 1107 for (i = 0; i < dpm_table->mclk_table.count; i++) { in tonga_populate_all_memory_levels()
1108 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in tonga_populate_all_memory_levels()
1113 dpm_table->mclk_table.dpm_levels[i].value, in tonga_populate_all_memory_levels()
1130 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in tonga_populate_all_memory_levels()
1131 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in tonga_populate_all_memory_levels()
1133 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in tonga_populate_all_memory_levels()
1498 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in tonga_program_memory_timing_parameters()
1501 data->dpm_table.mclk_table.dpm_levels[j].value, in tonga_program_memory_timing_parameters()
1545 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in tonga_populate_smc_boot_level()
2140 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { in tonga_convert_mc_reg_table_to_smc()
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