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Searched refs:mdp5_read (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_irq.c89 enable = mdp5_read(mdp5_kms, REG_MDP5_INTR_EN); in mdp5_irq()
90 status = mdp5_read(mdp5_kms, REG_MDP5_INTR_STATUS) & enable; in mdp5_irq()
Dmdp5_encoder.c265 return mdp5_read(mdp5_kms, REG_MDP5_INTF_LINE_COUNT(intf)); in mdp5_encoder_get_linecount()
274 return mdp5_read(mdp5_kms, REG_MDP5_INTF_FRAME_COUNT(intf)); in mdp5_encoder_get_framecount()
Dmdp5_crtc.c344 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm)); in blend_setup()
348 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm)); in blend_setup()
388 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm)); in mdp5_crtc_mode_set_nofb()
400 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm)); in mdp5_crtc_mode_set_nofb()
Dmdp5_ctl.c97 return mdp5_read(mdp5_kms, reg); in ctl_read()
107 intf_sel = mdp5_read(mdp5_kms, REG_MDP5_DISP_INTF_SEL); in set_display_intf()
Dmdp5_kms.h178 static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg) in mdp5_read() function
Dmdp5_kms.c552 version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION); in read_mdp_hw_revision()
Dmdp5_plane.c575 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) & in csc_disable()