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Searched refs:mmCP_CE_IC_BASE_HI (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c5346 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, in gfx_v10_0_rlc_backdoor_autoload_config_ce_cache()
5637 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, in gfx_v10_0_cp_gfx_load_ce_microcode()
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h10253 #define mmCP_CE_IC_BASE_HI … macro
Dgc_10_3_0_offset.h9863 #define mmCP_CE_IC_BASE_HI … macro