Home
last modified time | relevance | path

Searched refs:mmCP_DFY_CNTL (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/pm/inc/
Dpolaris10_pwrvirus.h53 { 0x80000004, mmCP_DFY_CNTL },
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dsmu7_smumgr.c512 cgs_write_register(hwmgr->device, mmCP_DFY_CNTL, section->dfy_cntl); in execute_pwr_dfy_table()
/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h175 #define mmCP_DFY_CNTL 0x3020 macro
Dgfx_7_2_d.h175 #define mmCP_DFY_CNTL 0x3020 macro
Dgfx_8_1_d.h197 #define mmCP_DFY_CNTL 0x3020 macro
Dgfx_8_0_d.h197 #define mmCP_DFY_CNTL 0x3020 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2298 #define mmCP_DFY_CNTL … macro
Dgc_9_1_offset.h2575 #define mmCP_DFY_CNTL … macro
Dgc_9_2_1_offset.h2513 #define mmCP_DFY_CNTL … macro