Home
last modified time | relevance | path

Searched refs:mmCP_HQD_HQ_STATUS0 (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_1_d.h664 #define mmCP_HQD_HQ_STATUS0 0x3265 macro
Dgfx_8_0_d.h664 #define mmCP_HQD_HQ_STATUS0 0x3265 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2885 #define mmCP_HQD_HQ_STATUS0 … macro
Dgc_9_1_offset.h3113 #define mmCP_HQD_HQ_STATUS0 … macro
Dgc_9_2_1_offset.h3069 #define mmCP_HQD_HQ_STATUS0 … macro
Dgc_10_1_0_offset.h5349 #define mmCP_HQD_HQ_STATUS0 … macro
Dgc_10_3_0_offset.h4982 #define mmCP_HQD_HQ_STATUS0 … macro