Searched refs:mmCP_ME_CNTL (Results 1 – 16 of 16) sorted by relevance
| /drivers/gpu/drm/amd/pm/inc/ |
| D | polaris10_pwrvirus.h | 51 { 0x15000000, mmCP_ME_CNTL },
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| /drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_6_0_d.h | 447 #define mmCP_ME_CNTL 0x21B6 macro
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| D | gfx_7_0_d.h | 505 #define mmCP_ME_CNTL 0x21b6 macro
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| D | gfx_7_2_d.h | 518 #define mmCP_ME_CNTL 0x21b6 macro
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| D | gfx_8_1_d.h | 571 #define mmCP_ME_CNTL 0x21b6 macro
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| D | gfx_8_0_d.h | 571 #define mmCP_ME_CNTL 0x21b6 macro
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v7_0.c | 2434 WREG32(mmCP_ME_CNTL, 0); in gfx_v7_0_cp_gfx_enable()
2436 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | in gfx_v7_0_cp_gfx_enable()
4682 …WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MA… in gfx_v7_0_soft_reset()
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| D | gfx_v6_0.c | 1955 WREG32(mmCP_ME_CNTL, 0); in gfx_v6_0_cp_gfx_enable()
1957 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | in gfx_v6_0_cp_gfx_enable()
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| D | gfx_v10_0.c | 5472 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); in gfx_v10_0_cp_gfx_enable()
5479 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v10_0_cp_gfx_enable()
5481 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v10_0_cp_gfx_enable()
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| D | gfx_v8_0.c | 4129 u32 tmp = RREG32(mmCP_ME_CNTL); in gfx_v8_0_cp_gfx_enable()
4140 WREG32(mmCP_ME_CNTL, tmp); in gfx_v8_0_cp_gfx_enable()
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| D | gfx_v9_0.c | 3133 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); in gfx_v9_0_cp_gfx_enable()
3138 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v9_0_cp_gfx_enable()
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| /drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 197 #define mmCP_ME_CNTL … macro
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| D | gc_9_1_offset.h | 197 #define mmCP_ME_CNTL … macro
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| D | gc_9_2_1_offset.h | 191 #define mmCP_ME_CNTL … macro
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| D | gc_10_1_0_offset.h | 2199 #define mmCP_ME_CNTL … macro
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| D | gc_10_3_0_offset.h | 2280 #define mmCP_ME_CNTL … macro
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