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Searched refs:mmCP_SC_PSINVOC_COUNT1_HI (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h539 #define mmCP_SC_PSINVOC_COUNT1_HI 0x212F macro
Dgfx_7_0_d.h400 #define mmCP_SC_PSINVOC_COUNT1_HI 0xc02f macro
Dgfx_7_2_d.h412 #define mmCP_SC_PSINVOC_COUNT1_HI 0xc02f macro
Dgfx_8_1_d.h448 #define mmCP_SC_PSINVOC_COUNT1_HI 0xc02f macro
Dgfx_8_0_d.h448 #define mmCP_SC_PSINVOC_COUNT1_HI 0xc02f macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h4629 #define mmCP_SC_PSINVOC_COUNT1_HI … macro
Dgc_9_1_offset.h4859 #define mmCP_SC_PSINVOC_COUNT1_HI … macro
Dgc_9_2_1_offset.h4815 #define mmCP_SC_PSINVOC_COUNT1_HI … macro
Dgc_10_1_0_offset.h7087 #define mmCP_SC_PSINVOC_COUNT1_HI … macro
Dgc_10_3_0_offset.h6716 #define mmCP_SC_PSINVOC_COUNT1_HI … macro