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Searched refs:mmD6VGA_CONTROL (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_timing_generator.c410 offset = mmD6VGA_CONTROL - mmD1VGA_CONTROL; in dce120_timing_generator_disable_vga()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_timing_generator.c1827 addr = mmD6VGA_CONTROL; in dce110_timing_generator_disable_vga()
/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h1046 #define mmD6VGA_CONTROL 0x00FB macro
Ddce_8_0_d.h5149 #define mmD6VGA_CONTROL 0xfb macro
Ddce_11_0_d.h6109 #define mmD6VGA_CONTROL 0xfb macro
Ddce_10_0_d.h6032 #define mmD6VGA_CONTROL 0xfb macro
Ddce_11_2_d.h7783 #define mmD6VGA_CONTROL 0xfb macro
Ddce_12_0_offset.h646 #define mmD6VGA_CONTROL … macro
/drivers/gpu/drm/amd/amdgpu/
Ddce_v8_0.c1747 mmD6VGA_CONTROL,
Ddce_v6_0.c1784 mmD6VGA_CONTROL,
Ddce_v10_0.c1818 mmD6VGA_CONTROL,
Ddce_v11_0.c1860 mmD6VGA_CONTROL,
/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h144 #define mmD6VGA_CONTROL … macro
Ddcn_1_0_offset.h456 #define mmD6VGA_CONTROL … macro
Ddcn_2_0_0_offset.h124 #define mmD6VGA_CONTROL … macro
Ddcn_3_0_0_offset.h105 #define mmD6VGA_CONTROL … macro