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Searched refs:mmDP0_DP_DPHY_CNTL (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h3117 #define mmDP0_DP_DPHY_CNTL 0x1CD0 macro
Ddce_8_0_d.h3868 #define mmDP0_DP_DPHY_CNTL 0x1cd0 macro
Ddce_11_0_d.h4478 #define mmDP0_DP_DPHY_CNTL 0x4aaf macro
Ddce_10_0_d.h4500 #define mmDP0_DP_DPHY_CNTL 0x4aaf macro
Ddce_11_2_d.h5710 #define mmDP0_DP_DPHY_CNTL 0x4aaf macro
Ddce_12_0_offset.h10224 #define mmDP0_DP_DPHY_CNTL … macro
/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h9881 #define mmDP0_DP_DPHY_CNTL … macro
Ddcn_1_0_offset.h8377 #define mmDP0_DP_DPHY_CNTL … macro
Ddcn_2_0_0_offset.h10974 #define mmDP0_DP_DPHY_CNTL … macro
Ddcn_3_0_0_offset.h10695 #define mmDP0_DP_DPHY_CNTL … macro