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Searched refs:mmGRBM_PWR_CNTL2 (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_1_offset.h80 #define mmGRBM_PWR_CNTL2 … macro
Dgc_9_0_offset.h89 #define mmGRBM_PWR_CNTL2 … macro
Dgc_9_1_offset.h89 #define mmGRBM_PWR_CNTL2 … macro
Dgc_9_2_1_offset.h87 #define mmGRBM_PWR_CNTL2 … macro
Dgc_10_1_0_offset.h2093 #define mmGRBM_PWR_CNTL2 … macro
Dgc_10_3_0_offset.h2168 #define mmGRBM_PWR_CNTL2 … macro